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Unformatted text preview: 5–1 E X E R C I S E S O L U T I O N S COMBINATIONAL LOGIC DESIGN PRINCIPLES 5 74LS138 G2A G1 G2B Y0 Y1 Y2 Y3 6 4 5 15 14 13 7 B A C Y4 Y5 Y6 Y7 1 12 11 10 9 2 3 5.4 READY ′ is an expression, with ′ being a unary operator. Use a name like READY_L or /READY instead. 5.8 Both LOWto HIGH and HIGHto LOW transitions cause positive transitions on the outputs of three gates (every second gate), and negative transitions on the other three. Thus, the total delay in either case is Since and for a 74LS00 are identical, the same result is obtained using a single worstcase delay of 15 ns. 5.12 The smallest typical delay through one ’LS86 for any set of conditions is 10 ns. Use the rule of thumb, “mini mum equals onefourth to onethird of typical,” we estimate 3 ns as the minimum delay through one gate. Therefore, the minimum delay through the four gates is estimated at 12 ns. The above estimate is conservative, as it does not take into account the actual transitions in the conditions shown. For a LOWto HIGH input transition, the four gates have typical delays of 13, 10, 10, and 20 ns, a total of 53 ns, so the minimum is estimated at onefourth of this or 13 ns. For a HIGHto LOW input transition, the four gates have typical delays of 20, 12, 12, and 13 ns, a total of 57 ns, so the minimum is estimated at 14 ns. 5.15 A decoder with activelow outputs ought to be faster, considering that this decoder structure can be imple mented directly with inverting gates (which are faster than noninverting) as shown in Figures 5–35 and 5–37. 5.16 The worstcase ’138 output will have a transition in the same direction as the worstcase ’139 output, so we use t pHL numbers for both, which is the worst combination. The delay through the ’139 is 38 ns, and from the t p 3 t pLH(LS00) 3 t pHL(LS00) + = 3 15 ⋅ 3 15 ⋅ + = 90 ns = t pLH t pHL 5–2 DIGITAL CIRCUITS activelow enable input of the ’138 is 32 ns, for a total delay of 70 ns. Using “worstcase” numbers for the parts and ignoring the structure of the circuit, an overly pessimistic result of 79 ns is obtained. We can also work the problem with 74HCT parts. Worstcase delay through the ’139 is 43 ns, and from the activelow enable input of the ’138 is 42 ns, for a total delay of 85 ns. Ignoring the structure of the circuit, an overly pessimistic result of 88 ns is obtained....
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 Spring '07
 Rucinska
 Berlin UBahn, odd parity, LSI, J. Wakerly

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