Homework08-sol

Homework08-sol - SOLUTION Homework #08 11/26/07 7:36PM...

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SOLUTION Homework #08 Cache characteristics 1. (15 points) The following quantitative data is available on cache performance: 11/26/07 7:36PM Cache Size (KB) Miss rate, 1-way Miss Rate, 2-way Miss Rate, 4-way Miss Rate, 8-way 1 0.191 0.161 0.152 0.149 2 0.148 0.122 0.115 0.113 4 0.109 0.095 0.087 0.084 8 0.087 0.069 0.065 0.063 16 0.066 0.054 0.049 0.048 32 0.05 0.041 0.038 0.038 64 0.039 0.03 0.028 0.028 128 0.026 0.02 0.016 0.015 a. (2) How are the cache size and the miss rate related? Bigger cache means lower miss rate. b (2) How are the associativity and the miss rate related? More associativity means lower miss rate. c(2) Does the miss rate decrease faster when the degree of associativity is doubled, or when the cache size is doubled? Doubling the cache size generally decreases the miss rate more. Grading: 2 pts for each correct answer, 1 for wrong but clear. d. (9) Consider a computer system with two levels of cache with the following specifications. Level 1 is 8Kbyte 4-way set associative cache that is on the same chip as the CPU, and has an access time of 5ns. Miss Rate 0.065 Level 2 is external to the CPU, and has an access time of 15ns. The main memory has an access time of 60 ns. The block size = 1 word for all caches Note: Here none of the access times include the access time of any previously accessed memory. For example, an external cache hit is (5+15)=20 ns. Using the quantitative data presented in the table above, determine the smallest Level 2 cache system that achieves an average access time that is less than 6.5 ns . Hints: Use a Decision tree table. First calculate the maximum allowable Level 2 miss rate 1-h 2 . Then search the above table. Case Weighted time (ns) 0.935 x 5 0.065 h 2 x (15+5) 0.065 x (1-h 2 )(60+15+5) C1-hit C1-miss C2-hit C2 miss Total 9.875 – 3.9 h 2 9,875 – 3.9 h 2 < 6.5 ms, therefore h 2 > ~0.865. The smallest cache with a miss ratio of < 0.135 is a 2KB 2-way, 4-way, or 8-way cache. ECE-562 Computer Organization, Fall 2007 Page 1 of 7
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A tree diagram for this problem: 0.935 0.065 L1 hit L1 miss 5 ns h 2 1-h 2 L2 hit L2 miss (15 + 5 ns) (60 + 15 + 5) ns Grading: 1 pt for every correct cell in the table, 3 for >0.95, 2 for selecting right associative cache or close equivalent. Cache addresses 2. ( 20 ) Consider a cache for a computer with 32-bit addresses. The memory system is byte addressable. The cache holds 512 Kbytes of data. Cache A is direct mapped, and has a block size of 4 bytes (1 word). Cache B is direct mapped, and has a block size of 16 bytes (4 words). The tag and the cache index together have just enough bits to identify each block. The following table lists a series of successive memory references as hex word addresses. Label each reference as a
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This homework help was uploaded on 04/08/2008 for the course ECE 562 taught by Professor Zhou during the Fall '07 term at New Hampshire.

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Homework08-sol - SOLUTION Homework #08 11/26/07 7:36PM...

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