t - Copyright(c 1995-2003 Xilinx Inc All Right Reserved...

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//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2003 Xilinx, Inc. // All Right Reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 7.1i // \ \ Application : ISE Foundation // / / Filename : t.tfw // /___/ /\ Timestamp : Fri Apr 30 16:13:51 2010 // \ \ / \ // \___\/\___\ // //Command: //Design Name: t //Device: Xilinx // `timescale 1ns/1ps module t; wire [3:0] an; wire a; wire b; wire c; wire d; wire e; wire f; wire g; reg clk = 1'b0; reg rst = 1'b0; parameter PERIOD = 20; parameter real DUTY_CYCLE = 0.5; parameter OFFSET = 100; initial // Clock process for clk begin #OFFSET; forever begin clk = 1'b0; #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1; #(PERIOD*DUTY_CYCLE); end end seg UUT ( .an(an), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .clk(clk), .rst(rst)); integer TX_FILE = 0; integer TX_ERROR = 0; initial begin // Open the results file... TX_FILE = $fopen("results.txt");
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#10020 // Final time: 10020 ns if (TX_ERROR == 0) begin $display("No errors or warnings."); $fdisplay(TX_FILE, "No errors or warnings."); end else begin $display("%d errors found in simulation.", TX_ERROR); $fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR); end $fclose(TX_FILE); $stop; end initial begin // ------------- Current Time: 105ns #105; rst = 1'b1; // ------------------------------------- // ------------- Current Time: 115ns #10; CHECK_a(1'b1); CHECK_b(1'b1); CHECK_c(1'b1);
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