sm - `timescale 1ns 1ps Company Engineer Create Date...

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`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 23:44:39 04/12/10 // Design Name: // Module Name: sm // Project Name: // Target Device: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module sm(clk, rst, bin,bout,a ); input clk; input rst; input bin; output bout; output a; reg bout,nxtbout; reg a,nxta,b,nxtb,c,nxtc,d,nxtd,e,nxte,f,nxtf,g,nxtg; [email protected](posedge clk or posedge rst)
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Unformatted text preview: begin if(rst) begin a<=1; b<=0; c<=0; d<=0; e<=0; f<=0; g<=0; bout<=0; end else begin a<=nxta; b<=nxtb; c<=nxtc; d<=nxtd; e<=nxte; f<=nxtf; g<=nxtg; bout<=nxtbout; end end [email protected](a or b or c or d or e or f or g or bin or bout ) begin if (f|g&~bin) nxta=1; else nxta=0; if (~bin&a) nxtb=1; else nxtb=0; if (bin&a) nxtc=1; else nxtc=0; if (~bin&b) nxtd=1; else nxtd=0; if (c|bin&b) nxte=1; else nxte=0; if (d|~bin&e) nxtf=1; else nxtf=0; if (e&bin) nxtg=1; else nxtg=0; if ((~bin&a)|(~bin&b)|(bin&c)|(~bin&e)|(~bin&g)|(bin&d)|(bin&f)) nxtbout=1; else nxtbout=0; end endmodule...
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  • Spring '07
  • Waqar

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