BCD2three - end end always(A or B or Bin or C or D or E or...

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// C:\XILINX\BCD2THREEEXCESS\UNTITLED.v // // Tue Dec 02 10:14:06 2008 // This Verilog code was made by Waqar Shahid Qureshi // // // `timescale 1s/1s module BCD2three(CLK,Bout,Bin,RESET,A); input CLK; input Bin,RESET; output Bout,A; reg Bout, next_Bout; reg A,next_A,B,next_B,C,next_C,D,next_D,E,next_E,F,next_F,G,next_G; always @(posedge CLK or posedge RESET) begin if ( RESET ) begin A <= 1; B <= 0; C <= 0; D <= 0; E <= 0; F <= 0; G <= 0; Bout <= 0; end else begin A <= next_A; B <= next_B; C <= next_C; D <= next_D; E <= next_E; F <= next_F; G <= next_G; Bout <= next_Bout;
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Unformatted text preview: end end always @ (A or B or Bin or C or D or E or F or G or Bout) begin if ( F | G & ~Bin ) next_A=1; else next_A=0; if ( ~Bin & A ) next_B=1; else next_B=0; if ( Bin & A ) next_C=1; else next_C=0; if ( ~Bin & B ) next_D=1; else next_D=0; if (C | Bin & B) next_E=1; else next_E=0; if ( D | ~Bin & E ) next_F=1; else next_F=0; if ( E & Bin) next_G=1; else next_G=0; if ( ~Bin & A | ~Bin & B | Bin & C | ~Bin & E | ~Bin & G | Bin & D | Bin & F ) next_Bout=1; else next_Bout=0; end endmodule...
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