Serial_to_parallel - output[3:0 Bout_parallel input clk...

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`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 22:43:15 12/02/08 // Design Name: // Module Name: Serial-to_parallel // Project Name: // Target Device: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module Serial_to_parallel(Bout_serial, Bout_parallel, clk, rst); input Bout_serial;
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Unformatted text preview: output [3:0] Bout_parallel; input clk; input rst; wire Bout_serial; reg [3:0] Bout_parallel; reg [2:0] count; reg [4:0] Bout_p; always @(posedge clk or posedge rst) begin if(rst) begin Bout_parallel <=0; Bout_p <= 0; count <=0; end else if (count<5) begin Bout_p[count] <=Bout_serial; count <=count +1; end else if(count==5) begin Bout_parallel[3] <= Bout_p[4]; Bout_parallel[2] <= Bout_p[3]; Bout_parallel[1] <= Bout_p[2]; Bout_parallel[0] <= Bout_p[1]; end else Bout_parallel <= 4'bz; end endmodule...
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