testbench - wire d wire e wire f wire g Instantiate the...

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`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 09:17:30 03/07/2010 // Design Name: sidra // Module Name: testbench.v // Project Name: bcd2sevensegment // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: sidra // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module testbench_v; // Inputs reg w; reg x; reg y; reg z; // Outputs wire a; wire b; wire c;
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Unformatted text preview: wire d; wire e; wire f; wire g; // Instantiate the Unit Under Test (UUT) sidra uut ( .w(w), .x(x), .y(y), .z(z), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g) ); initial begin w = 0;x = 0;y = 0;z = 0; #10 w = 0;x = 0;y = 0;z = 1; #10 w = 0;x = 0;y = 1;z = 0; #10 w = 0;x = 0;y = 1;z = 1; #10 w = 0;x = 1;y = 0;z = 0; #10 w = 0;x = 1;y = 0;z = 1; #10 w = 0;x = 1;y = 1;z = 0; #10 w = 0;x = 1;y = 1;z = 1; #10 w = 1;x = 0;y = 0;z = 0; #10 w = 1;x = 0;y = 0;z = 1; end initial $monitor("w=%b,x=%b,y=%b,z=%b,a=%b,b=%b,c=%b,d=%b,e=%b,f=%b,g= %b",w,x,y,z,a,b,c,d,e,f,g); endmodule...
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