test - reg s_row reg clk reg rst Outputs wire[3:0 code...

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`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 19:40:35 05/19/2010 // Design Name: mariam // Module Name: test.v // Project Name: scanner // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: mariam // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module test_v; // Inputs reg [3:0] row;
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Unformatted text preview: reg s_row; reg clk; reg rst; // Outputs wire [3:0] code; wire [3:0] col; wire valid; // Instantiate the Unit Under Test (UUT) mary m1 ( .code(code), .col(col), .valid(valid), .row(row), .s_row(s_row), .clk(clk), .rst(rst) ); row_signal m2(row,key,col); synchronizer m3(s_row,row,clk,rst); initial #2000 $finish; initial begin clk=0; forever #5 clk=~clk; end initial begin rst=1; #10 rst=0; end initial begin #10 s_row=1; wait(col==4'b1000) row=4'b0010; end initial $monitor("row=%b,col=%b,code=%b",row,col,code); endmodule...
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