Final Exam Solution Fall 2010 on Introduction to Digital Logic and Computer Design

Final Exam Solution Fall 2010 on Introduction to Digital Logic and Computer Design

This preview shows page 1 - 5 out of 11 pages.

- 1 - 1. (10 points). Define combinational circuit. A combinational circuit is one in which the circuit’s outputs depend only on the current value of the inputs. Is the circuit implemented by the VHDL module shown below a combinational circuit circuit? Explain your answer. entity foo is port( A, B, C: in std_logic; Z: out: std_logic; end entity; architecture a1 of foo signal X: std_logic; begin process(A, B, C) begin if A > B then X <= C; elsif A = X then X <= A or C; end if; end process; Z <= X and B; end; This circuit is not a combinational circuit. There is no assignment to the signal X corresponding to the condition A<B. Consequently, when this condition occurs, X will retain its current value. This behavior is implemented using a latch for the signal X. Consequently, the input sequence ABC=100, 010 results in Z=0, while the sequence ABC=101,010 leaves Z=1. This contradicts the definition of a combinational circuit. CSE 260 – Digital Computers: Organization and Logical Design Final Exam Solutions Jon Turner
Image of page 1

Subscribe to view the full document.

- 2 - 2. (15 points) The VHDL module shown below defines a sequential circuit that looks for the minimum value present on the input A and counts the number of clock periods when this minimum value is present. It has two outputs, minVal and minCount . So for example, if the input sequence on A is 57, 85, 23, 34, 36, 23, 46, 23 then the sequences of values on the two two outputs will be 57, 57, 23, 23, 23, 23, 23, 23 and 1,1,1,1,1,2,2,3. entity minValCount is port ( clk, reset: in std_logic; A : in std_logic_vector(7 downto 0); minVal, minCount : out std_logic_vector(7 downto 0)); end minValCount; architecture a1 of minValCount is signal val, count: std_logic_vector(7 downto 0); begin process (clk) begin if rising_edge(clk) then if reset = '1' then val <= x”FF”; count <= x”00”; else if A < val then val <= A; count <= x”01”; elsif A = val then count <= count + 1; end if; end if; end if; end process; minVal <= val; minCount <= count; end a1;
Image of page 2
- 3 -
Image of page 3

Subscribe to view the full document.

- 4 - 3. (10 points) The simulation output shows a program executing on the WashU-2 processor. Fill in the blanks below with the information that belongs in each of the labeled blank areas in the simulation. A. 1FFF B . FFFF C . 0002 D. 5224 E . 1208 The instruction set for the processor appears below.
Image of page 4
Image of page 5
  • Fall '09
  • Logic gate, Combinational Circuit, std_logic

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern