Final Exam Spring 2007 on Introduction to Digital Logic and Computer Design

# Final Exam Spring 2007 on Introduction to Digital Logic and Computer Design

• Test Prep
• ChefLightningHawk2957
• 12

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- 1 - 1. (10 points) Draw a transistor-level diagram (using n -FETs and p -FETs) of a CMOS NOR gate with 3 inputs, A , B and C . Suppose all three inputs are low initially and then one A goes high, causing the output of the NOR gate to go from high to low. Let t HL be the time for this high to low transition. Now, suppose that input A goes low again, causing the output to go from low to high. Let t LH be the time for this low to high transition. Which is larger, t LH or t HL ? Explain why. How much larger? Assume that the on-resistance of an n -FET is the same as the on- resistance of a p -FET. CSE 260 – Digital Computers: Organization and Logical Design Final Exam Jon Turner 5/3/2007

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- 2 - 2. (10 points) Use Karnaugh maps to derive a minimal sum of products expression and a minimal product of sums expression for the function. F ( A , B , C,D ) = Σ m (0,4,5,12), d ( A , B , C,D ) = Σ m (3,7,8,11,13,14). Make full use of the don’t care conditions. How many simple gates AND gates, OR gates and inverters are needed to implement circuits for the simpler of the two expressions you derived? If CMOS gates are used in these circuits, how many transistors do they contain?
- 3 - 3. (15 points) Draw a logic diagram that directly corresponds to the VHDL module shown below. Every signal that appears in the VHDL should be labeled in your logic diagram. Your logic diagram may include gates, flip flops and multiplexors. entity foo is port ( clk, enable: in std_logic; A, B : in std_logic; X: out std_logic); end foo; architecture a1 of foo is signal s0, s1: std_logic; begin process(clk) begin if rising_edge(clk) then if enable = ‘0’ then s0 <= ‘0’; s1 <= ‘0’; else if s0 = ‘1’ and A = ‘1’ then s1 <= s0; elsif s0 > s1 then s0 <= A xor B; end if; end if; end if; end process; X <= ‘1’ when s1 > B else ‘0’; end a1;

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- 4 - 4. (20 points) The circuit shown below is a 3 digit BCD maximum circuit. The output max (2..0) is equal to the larger of A (2..0) and B (2..0). Estimate the number of 4 input LUTs needed to implement one section of this circuit. Justify your estimate.
• Fall '09
• Logic gate, std_logic, VHDL module, architecture a1

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