Final Exam Spring 2007 on Introduction to Digital Logic and Computer Design

Final Exam Spring 2007 on Introduction to Digital Logic and Computer Design

This preview shows page 1 - 5 out of 12 pages.

- 1 - 1. (10 points) Draw a transistor-level diagram (using n -FETs and p -FETs) of a CMOS NOR gate with 3 inputs, A , B and C . Suppose all three inputs are low initially and then one A goes high, causing the output of the NOR gate to go from high to low. Let t HL be the time for this high to low transition. Now, suppose that input A goes low again, causing the output to go from low to high. Let t LH be the time for this low to high transition. Which is larger, t LH or t HL ? Explain why. How much larger? Assume that the on-resistance of an n -FET is the same as the on- resistance of a p -FET. CSE 260 – Digital Computers: Organization and Logical Design Final Exam Jon Turner 5/3/2007
Image of page 1

Subscribe to view the full document.

- 2 - 2. (10 points) Use Karnaugh maps to derive a minimal sum of products expression and a minimal product of sums expression for the function. F ( A , B , C,D ) = Σ m (0,4,5,12), d ( A , B , C,D ) = Σ m (3,7,8,11,13,14). Make full use of the don’t care conditions. How many simple gates AND gates, OR gates and inverters are needed to implement circuits for the simpler of the two expressions you derived? If CMOS gates are used in these circuits, how many transistors do they contain?
Image of page 2
- 3 - 3. (15 points) Draw a logic diagram that directly corresponds to the VHDL module shown below. Every signal that appears in the VHDL should be labeled in your logic diagram. Your logic diagram may include gates, flip flops and multiplexors. entity foo is port ( clk, enable: in std_logic; A, B : in std_logic; X: out std_logic); end foo; architecture a1 of foo is signal s0, s1: std_logic; begin process(clk) begin if rising_edge(clk) then if enable = ‘0’ then s0 <= ‘0’; s1 <= ‘0’; else if s0 = ‘1’ and A = ‘1’ then s1 <= s0; elsif s0 > s1 then s0 <= A xor B; end if; end if; end if; end process; X <= ‘1’ when s1 > B else ‘0’; end a1;
Image of page 3

Subscribe to view the full document.

- 4 - 4. (20 points) The circuit shown below is a 3 digit BCD maximum circuit. The output max (2..0) is equal to the larger of A (2..0) and B (2..0). Estimate the number of 4 input LUTs needed to implement one section of this circuit. Justify your estimate.
Image of page 4
Image of page 5
  • Fall '09
  • Logic gate, std_logic, VHDL module, architecture a1

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern