- 1 - 1.(10 points) List the minterms and maxterms for the expression A′B+ (A + B′)C+ (A+C)′B?
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2.(10 points) For each VHDL code fragment shown below, write an equivalent set of simple signal assignments (each involving just a single signal, not a vector of signals). (a) a <= ‘1’; b <= x xor z; case c is when “00” => a <= x or y; when “01” => b <= y; when others => a <= c(1); end case; (b)x <= c; for i in 0 to 2 loop z(i) <= a(i) xor x; x <= (not a(i)) or x; end loop;
- 3 - 3.(10 points) The simulation output shows selected signals from the processor introduced in section 1 of the course notes. The portions of the output corresponding to four different instructions are outlined. Note that some parts of the simulation output have been blanked out. For the labeled blanks, fill in the missing information below.
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