Quiz 3 Fall 2010 on Introduction to Digital Logic and Computer Design

Quiz 3 Fall 2010 on Introduction to Digital Logic and Computer Design

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- 1 - 1. (5 points) Given the following signal declarations. signal x: std_logic_vector(19 downto 0); signal y: std_logic_vector(3 to 10); What is the value of x’right ? What is the value of y’high ? What is the value of x’range ? Write a VHDL assignment statement that makes the std_logic_vector z equal to 7, without assuming any specific width for z . You may assume that the index range for z is descending ( downto ) and that z’right =0. CSE 260 – Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 10/12/2010
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- 2 - 2. (5 points) The VHDL code below is from the testbench for the BCD adder that was discussed in the lecture notes. Suppose that when the A and B inputs are “0101” and “0100”
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Unformatted text preview: and cIn =’1’ the circuit produces a sum output of “0101” and cOut =‘0’. Put an ‘X’ next to all the assertions that fail in this case. uut: bcdAdd port map(A,B,sum,cIn,cOut); process variable s: integer; begin for i in 0 to 1 loop for j in 0 to 9 loop for k in 0 to 9 loop if i = 0 then cIn <= '0'; else cIn <= '1'; end if; A <= conv_std_logic_vector(j,4); B <= conv_std_logic_vector(k,4); s := i + j + k; wait for pause; assert (x"0" <= sum and sum <= x"9") report . .. assert (s <= 9 or cOut = '1') report . .. assert (s >= 10 or cOut = '0') report . .. assert (s >= 10 or int(sum) = s) report . .. assert (s <= 9 or int(sum) = s - 10) report . .. end loop; end loop; end loop;...
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  • Fall '09
  • Equals sign, VHDL assignment statement, Jon Turner, following signal declarations

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