**Unformatted text preview: **and cIn =’1’ the circuit produces a sum output of “0101” and cOut =‘0’. Put an ‘X’ next to all the assertions that fail in this case. uut: bcdAdd port map(A,B,sum,cIn,cOut); process variable s: integer; begin for i in 0 to 1 loop for j in 0 to 9 loop for k in 0 to 9 loop if i = 0 then cIn <= '0'; else cIn <= '1'; end if; A <= conv_std_logic_vector(j,4); B <= conv_std_logic_vector(k,4); s := i + j + k; wait for pause; assert (x"0" <= sum and sum <= x"9") report . .. assert (s <= 9 or cOut = '1') report . .. assert (s >= 10 or cOut = '0') report . .. assert (s >= 10 or int(sum) = s) report . .. assert (s <= 9 or int(sum) = s - 10) report . .. end loop; end loop; end loop;...

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- Fall '09
- Equals sign, VHDL assignment statement, Jon Turner, following signal declarations