Midterm Exam Spring 2008 on Introduction to Digital Logic and Computer Design

Midterm Exam Spring 2008 on Introduction to Digital Logic and Computer Design

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- 1 - 1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items blanked out. Fill in the blanks below with the correct value from the corresponding labeled blank in the simulation output. The instruction set appears at the bottom of the page. A . ______________ B . ______________ C . ______________ D . ______________ E . ______________ 0000 halt 0001 negate 1xxx immediate load 2xxx direct load 3xxx indirect load 4xxx direct store 5xxx indirect store 6xxx branch 7xxx branch if zero 8xxx branch if positive 9xxx branch if negative axxx add dxxx and CSE 260 – Digital Computers: Organization and Logical Design Midterm Jon Turner 2/28/2008
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- 2 - 2. (8 points) Draw a transistor-level diagram (using n -FETs and p -FETs) of a NAND gate with 3 inputs, A , B and C . Suppose all three inputs are high initially and then A goes low, causing the output of the NAND gate to go from low to high. Let t LH be the time for this high to low transition. Now, suppose that input A goes high again, causing the output to go from high to low. Let t HL be the time for this low to high transition. Which is larger, t LH or t HL ? Explain why. How much larger? Assume that the on-resistance of an n -FET is the same as the on- resistance of a p -FET.
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- 3 - 3. (6 points) The circuit shown below is a 4 bit adder, implemented using LUT4s. The outputs
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  • Fall '09
  • Logic gate, pulse pair

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