Module 10 HW.docx - Module#10 Homework Questions(10 pts...

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Module #10 Homework Questions (10 pts each) Table 1: MIPS Processing Stages & times Processing Stage Instr. Instr. Fetch (IF) Register read (ID/Reg) ALU (EX/ALU) Memory access (MEM/ Data Access) Register writeback (WB/ Reg) Total time lw 350ps 125 ps 200ps 450ps 125ps 1250ps sw 350ps 125 ps 200ps 450ps N/A 1125ps R-format 350ps 125 ps 200ps N/A 125ps 800ps beq 350ps 125 ps 200ps N/A N/A 675ps 1) Assuming a 5-Stage MIPS processor, what is the minimum clock cycle that can supported?
2) What factors determine the minimum clock cycle for a 5-Stage MIPS processor?
Show the processing timeline of the 5-Stage MIPS processor for the follow MIPS ASM instructions and the total execution time (ignoring hazards) .data .text
3) Show the processing timeline of a 5 Stage processor for the above instructions (ignoring

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