# L14 - CS 61C L14 MIPS Instruction Representation II (1)...

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Unformatted text preview: CS 61C L14 MIPS Instruction Representation II (1) Wawrzynek Fall 2007 UCB 9/28/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C Machine Structures Lecture 14 - MIPS Instruction Representation II CS 61C L14 MIPS Instruction Representation II (2) Wawrzynek Fall 2007 UCB Alternatives to Immediates Are immediates really needed? Is it possible to invent an ISA (instruction set architecture) without immediates? If so, what would be the consequences? CS 61C L14 MIPS Instruction Representation II (3) Wawrzynek Fall 2007 UCB I-Format Problem (1/3) Problem: Chances are that addi , lw , sw and slti will use immediates small enough to ft in the immediate feld. but what i it s too big? We need a way to deal with a 32-bit immediate in any I-ormat instruction. CS 61C L14 MIPS Instruction Representation II (4) Wawrzynek Fall 2007 UCB I-Format Problem (2/3) Solution to Problem: Handle it in sotware + new instruction Don t change the current instructions: instead, add a new instruction to help out New instruction: lui register, immediate stands or L oad U pper I mmediate takes 16-bit immediate and puts these bits in the upper hal (high order hal) o the specifed register sets lower hal to 0s CS 61C L14 MIPS Instruction Representation II (5) Wawrzynek Fall 2007 UCB I-Format Problems (3/3) Solution to Problem (continued): So how does lui help us? Example: addi \$t0,\$t0, 0xABABCDCD becomes: lui \$at, 0xABAB ori \$at, \$at, 0xCDCD add \$t0,\$t0,\$at Now each I-format instruction has only a 16- bit immediate. Wouldn t it be nice if the assembler would this for us automatically? (later) CS 61C L14 MIPS Instruction Representation II (6) Wawrzynek Fall 2007 UCB Branches: PC-Relative Addressing (1/5) Use I-Format opcode rs rt immediate opcode species beq versus bne rs and rt specify registers to compare What can immediate specify?...
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## L14 - CS 61C L14 MIPS Instruction Representation II (1)...

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