L28 - CS61C L28 SIngle Cycle CPU 2 Wawrzynek, Fall 2007 UCB...

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Unformatted text preview: CS61C L28 SIngle Cycle CPU 2 Wawrzynek, Fall 2007 UCB 10/31/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C Machine Structures Lecture 28 - Single Cycle CPU Design, Part II 1 CS61C L28 SIngle Cycle CPU 2 Wawrzynek, Fall 2007 UCB How to Design a Processor: step-by- 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic 2 CS61C L28 SIngle Cycle CPU 2 Wawrzynek, Fall 2007 UCB Peer Instruction A. In the CPU presented, if the destination reg is the same as the source reg, we could compute the incorrect value. B. For the single cycle CPU, the controller circuit is a Finite State Machine. C. In a single-cycle CPU the ALU could be used more than once for some instructions. ABC 0: FFF 1: FF T 2: F T F 3: F TT 4: T FF 5: T F T 6: TT F 7: TTT 3 CS61C L28 SIngle Cycle CPU 2 Wawrzynek, Fall 2007 UCB Clocking Methodology Storage elements clocked by same edge Combinational logic has delays Being physical devices, ip-ops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay...
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This note was uploaded on 04/09/2008 for the course CS 61A taught by Professor Harvey during the Spring '08 term at University of California, Berkeley.

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L28 - CS61C L28 SIngle Cycle CPU 2 Wawrzynek, Fall 2007 UCB...

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