This preview shows pages 1–4. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: CS61c: Representations of Combinational Logic Circuits J. Wawrzynek March 5, 2003 1 Introduction Recall that synchronous systems are composed of two basic types of circuits, combination logic circuits, and state elements. Combination logic circuits without memory that produce outputs based purely on their input signals. State elements, on the other hand, are circuits that remember their input signal values. In the previous lecture we looked at the internal details of registers. We found that every register, regardless of its use has the same internal structure. Combinational logic (CL) blocks, on the other hand, are all different from one another. The internal circuit structure of each is tailored to the functional requirements of that particular circuit. In this lecture we will look at three different ways to represent the function and structure of a combination logic block. 2 TruthTables Combinational logic circuit behavior can be specified by enumerating the functional relationship be tween input values and output values. For each input pattern of 1s and 0s applied to the CL circuit block, there exists a single output pattern. This input/output relationship is commonly enumerated in a tabular form, called a truthtable . In general, a truthtable takes the form shown below. Below is the general form for a truthtable representing a circuit block with four inputs: 1 2 Wawrzynek 2003 c UCB a b c d y F(0,0,0,0) 1 F(0,0,0,1) 1 F(0,0,1,0) 1 1 F(0,0,1,1) 1 F(0,1,0,0) 1 1 F(0,1,0,1) 1 1 F(0,1,1,0) 1 1 1 1 F(0,1,1,1) 1 F(1,0,0,0) 1 1 F(1,0,0,1) 1 1 F(1,0,1,0) 1 1 1 F(1,0,1,1) 1 1 F(1,1,0,0) 1 1 1 F(1,1,0,1) 1 1 1 F(1,1,1,0) 1 1 1 1 F(1,1,1,1) For each row of the table, the output column shows the output value of the block for the input pattern shown in the input columns. Many CL blocks have more than one output, or a single output that is more than one bit wide. In these cases, each single bit output gets its own truthtable. Often they are combined into a single table with multiple output columns, one for each single bit output. Below are some example truthtables: 1. Consider a CL block with two inputs, a & b, and a single output y. The output y has value 1 if one, but not both, of the inputs is a 1. a b y 1 1 1 1 1 1 CS61c Lecture Notes 3 2. A 2bit wide unsigned adder circuit with a 3bit wide output: A B C a 1 a b 1 b c 2 c 1 c 00 00 000 00 01 001 00 10 010 00 11 011 01 00 001 01 01 010 01 10 011 01 11 100 10 00 010 10 01 011 10 10 100 10 11 101 11 00 011 11 01 100 11 10 101 11 11 110 3. 32bit unsigned adder with 33bit output: A B C 000 ... 0 000 ... 0 000 ... 00 000 ... 0 000 ... 1 000 ... 01 . . . . . . . . . 111 ... 1 111 ... 1 111 ... 10 This table has 2 6 4 rows!...
View Full
Document
 Spring '08
 Harvey

Click to edit the document details