L29 - CS61C Machine Structures Lecture 29 - Single Cycle...

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CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB 11/2/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C – Machine Structures Lecture 29 - Single Cycle CPU Controller Design 1 CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr clk busW RegWr 32 32 busA 32 busB 5 5 Rw Ra Rb RegFile Rs Rt Rt Rd RegDst Extender 32 16 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr Equal Instruction<31:0> <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs clk PC 00 4 nPC_sel PC Ext Adr Inst Memory Adder Mux 0 1 0 1 = ALU 0 1 WrEn Adr Data Memory 5 2
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CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB An Abstract View of the Implementation Data Out clk 5 Rw Ra Rb Register File Rd Data In Data Addr Ideal Data Memory Instruction Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 32 32 32 A B Next Address Control Datapath Control Signals Conditions clk clk ALU 3 CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB Recap: Meaning of the Control ° nPC_sel : “+4” 0 PC <– PC + 4 “br” 1 PC <– PC + 4 + {SignEx(Im16) , 00 } “n” = n ext imm16 clk 00 4 nPC_sel PC Ext Adder Mux Inst Address 0 1 4
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CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB Recap: Meaning of the Control ° ExtOp: “zero”, “sign” ° ALUsrc: 0 regB; 1 immed ° ALUctr: ADD ”, “ SUB ”, “ OR ° MemWr: 1 write memory ° MemtoReg: 0 ALU; 1 Mem ° RegDst: 0 “rt”; 1 “rd” ° RegWr: 1 write register 32 ALUctr clk busW RegWr 32 32 busA 32 busB 5 5 Rw Ra Rb RegFile Rs Rt Rt Rd RegDst Extender 32 16 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 0 1 0 1 ALU 0 1 WrEn Adr Data Memory 5 5 CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB The Single Cycle Datapath during Add R[rd] = R[rs] + R[rt] 32 ALUctr= ADD clk busW RegWr=1 32 32 busA 32 busB 5 5 Rw Ra Rb RegFile Rs Rt Rt Rd RegDst=1 32 16 imm16 ALUSrc=0 ExtOp=x MemtoReg=0 clk Data In 32 MemWr=0 zero 0 1 0 1 = 0 1 WrEn Adr Data Memory 5 Instruction<31:0> <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs nPC_sel=+4 instr fetch unit clk 6 op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits
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CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB Instruction Fetch Unit at the End of Add PC = PC + 4 •This is the same for all instructions except: Branch and Jump imm16 clk PC 00 4 nPC_sel=+4 PC Ext Adder Mux Inst Address Inst Memory 7 CS61C L29 SIngle Cycle CPU Control Wawrzynek, Fall 2007 © UCB Single Cycle Datapath during Or Immediate?
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This note was uploaded on 04/09/2008 for the course CS 61A taught by Professor Harvey during the Spring '08 term at University of California, Berkeley.

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L29 - CS61C Machine Structures Lecture 29 - Single Cycle...

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