L27 - CS61C Machine Structures Lecture 27 - Single Cycle...

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CS61C L27 SIngle Cycle CPU Wawrzynek, Fall 2007 © UCB 10/29/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C – Machine Structures Lecture 27 - Single Cycle CPU Design, Part I 1 CS61C L27 SIngle Cycle CPU Wawrzynek, Fall 2007 © UCB Datapath Summary The datapath based on data transfers required to perform instructions A controller causes the right transfers to happen PC instruction memory + 4 rt rs rd registers ALU Data imm Controller opcode, funct 2
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CS61C L27 SIngle Cycle CPU Wawrzynek, Fall 2007 © UCB CPU clocking (1/2) Single Cycle CPU : All stages of an instruction are completed within one long clock cycle. • The clock cycle is made sufficient long to allow each instruction to complete all stages without interruption and within one cycle. For each instruction, how do we control the flow of information though the datapath? 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write 3 CS61C L27 SIngle Cycle CPU Wawrzynek, Fall 2007 © UCB CPU clocking (2/2) Multiple-cycle CPU : Only one stage of instruction per clock cycle. • The clock is made as long as the slowest stage. Several significant advantages over single cycle execution: Unused stages in a particular instruction can be skipped OR instructions can be pipelined (overlapped). For each instruction, how do we control the flow of information though the datapath? 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write 4
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CS61C L27 SIngle Cycle CPU Wawrzynek, Fall 2007 © UCB Peer Instruction A. In the single cycle CPU , we re going to be able to read 2 registers and write a 3 rd in 1 cycle B. In the non-pipelined multi-cycle CPU , the average time to execute an instruction is likely to be more than with the single- cycle design. C. If the delay through a 1-bit adder is T, then the delay through our N-bit wide ALU will be N * T ABC 0: FFF 1: FF T 2: F T F 3: F TT 4: T FF 5: T F T 6: TT F 7: TTT 5 CS61C L27 SIngle Cycle CPU Wawrzynek, Fall 2007 © UCB How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) datapath requirements •meaning of each instruction is given by the data transfers (register transfers) •datapath must include storage element for ISA registers
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L27 - CS61C Machine Structures Lecture 27 - Single Cycle...

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