# L24 - CS61C Machine Structures Lecture 24 - ALU Design and...

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1 CS61C L24 ALU Wawrzynek, Fall 2007 © UCB 1 10/22/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C – Machine Structures Lecture 24 - ALU Design and More Verilog CS61C L24 ALU Wawrzynek, Fall 2007 © UCB 2 Review: Representations for CL Use this diagram and techniques we learned to transform from one to another ° In practice, useful only for small blocks. Cut block into smaller pieces (hierarchy) Rely on Computer Aided Design Tools (logic synthesis). Generate Canonical Form Optimize Logic Equations

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2 CS61C L24 ALU Wawrzynek, Fall 2007 © UCB 3 Arithmetic and Logic Unit Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU) We’ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR CS61C L24 ALU Wawrzynek, Fall 2007 © UCB 4 One Approach to Simple ALU
3 CS61C L24 ALU Wawrzynek, Fall 2007 © UCB 5 Adder/Subtracter Design -- how? Truth-table, then determine canonical form, then minimize and implement. ° Look at breaking the problem down into

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## This note was uploaded on 04/09/2008 for the course CS 61A taught by Professor Harvey during the Spring '08 term at Berkeley.

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L24 - CS61C Machine Structures Lecture 24 - ALU Design and...

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