L30 - CS61C L30 Processor Pipelining I Wawrzynek, Fall 2007...

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Unformatted text preview: CS61C L30 Processor Pipelining I Wawrzynek, Fall 2007 UCB 11/5/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C Machine Structures Lecture 30 - Processor Pipelining I 1 CS61C L30 Processor Pipelining I Wawrzynek, Fall 2007 UCB 5 steps to design a processor 1. Analyze instruction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Control is the hard part MIPS makes that easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Review: Single cycle datapath Control Datapath Memory Processor Input Output 2 CS61C L30 Processor Pipelining I Wawrzynek, Fall 2007 UCB How We Build The Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw nPCsel = beq Jump = jump ExtOp = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR) ALUctr[1] = or where, rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op 1 ~op , ori = ~op 5 ~op 4 op 3 op 2 ~op 1 op lw = op 5 ~op 4 ~op 3 ~op 2 op 1 op sw = op 5 ~op 4 op 3 ~op 2 op 1 op beq = ~op 5 ~op 4 ~op 3 op 2 ~op 1 ~op jump = ~op 5 ~op 4 ~op 3 ~op 2 op 1 ~op add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func 1 ~func sub = rtype func 5 ~func 4 ~func 3 ~func 2 func 1 ~func How do we implement this in gates? add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0] ALUctr[1] AND logic OR logic opcode func 3 CS61C L30 Processor Pipelining I Wawrzynek, Fall 2007 UCB Processor Performance Can we estimate the clock rate (frequency) of our single-cycle processor? We know: 1 cycle per instruction lw is the most demanding instruction....
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This note was uploaded on 04/09/2008 for the course CS 61A taught by Professor Harvey during the Spring '08 term at University of California, Berkeley.

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L30 - CS61C L30 Processor Pipelining I Wawrzynek, Fall 2007...

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