L31 - CS61C Machine Structures Lecture 31 - Processor...

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CS61C L31 CPU Pipelining II (1) Wawrzynek, Fall 2007 © UCB 11/7/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C – Machine Structures Lecture 31 - Processor Pipelining II CS61C L31 CPU Pipelining II (2) Wawrzynek, Fall 2007 © UCB Review: Processor Pipelining (1/2) “Pipeline registers” are added to the datapath/controller to neatly divide the single cycle processor into “pipeline stages”. Optimal Pipeline Each stage is executing part of an instruction each clock cycle. One inst. finishes during each clock cycle. On average, execute far more quickly. What makes this work well? Similarities between instructions allow us to use same stages for all instructions (generally). Each stage takes about the same amount of time as all others: little wasted time.
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CS61C L31 CPU Pipelining II (3) Wawrzynek, Fall 2007 © UCB Review: Pipeline (2/2) Pipelining is a BIG IDEA widely used concept What makes it less than perfect? Structural hazards : Conflicts for resources. Suppose we had only one cache? Need more HW resources Control hazards : Branch instructions effect which instructions come next. Delayed branch Data hazards : Data flow between instructions. CS61C L31 CPU Pipelining II (4) Wawrzynek, Fall 2007 © UCB Control Hazard: Branching (1/8) Where do we do the compare for the branch? I$ beq Instr 1 Instr 2 Instr 3 Instr 4 ALU I$ Reg D$ Reg I$ Reg D$ Reg I$ Reg D$ Reg Reg D$ Reg I$ Reg D$ Reg I n s t r. O r d e r Time (clock cycles)
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L31 CPU Pipelining II (5) Wawrzynek, Fall 2007 © UCB Control Hazard: Branching (2/8) We had put branch decision-making hardware in ALU stage therefore two more instructions after the branch will always be fetched, whether or not the branch is taken Desired functionality of a branch if we do not take the branch, don t waste any time and continue executing normally if we take the branch, don t execute any instructions after the branch, just go to the desired label CS61C L31 CPU Pipelining II (6) Wawrzynek, Fall 2007 © UCB Control Hazard: Branching (3/8) Initial Solution: Stall until decision is made insert “no-op” instructions (those that accomplish nothing, just take time) or hold up the fetch of the next instruction (for 2 cycles). Drawback: branches take 3 clock cycles
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L31 - CS61C Machine Structures Lecture 31 - Processor...

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