L34 - CS61C Machine Structures Lecture 34 - Caches II...

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CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB 11/16/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C – Machine Structures Lecture 34 - Caches II 1 CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB What to do on a write hit? Write-through • update the word in cache block and corresponding word in memory Write-back • update word in cache block • allow memory word to be “stale” add ʻ dirty ʼ bit to each block indicating that memory needs to be updated when block is replaced OS fushes cache be±ore I/O… Per±ormance trade-o±±s? 2 Two Options:
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CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB Block Size Tradeoff (1/3) Bene±ts of Larger Block Size Spatial Locality : if we access a given word, we ʼ re likely to access other nearby words soon • Very applicable with Stored-Program Concept: if we execute a given instruction, it ʼ s likely that we ʼ ll execute the next few as well • Works nicely in sequential array accesses too 3 CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB Block Size Tradeoff (2/3) Drawbacks of Larger Block Size • Larger block size means larger miss penalty on a miss, takes longer time to load a new block from next level • If block size is too big relative to cache size, then there are too few blocks Result: miss rate goes up In general, minimize Average Memory Access Time (AMAT) = Hit Time + Miss Penalty x Miss Rate 4
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CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB Block Size Tradeoff (3/3) Hit Time = time to ±nd and retrieve data from current level cache Miss Penalty = average time to retrieve data on a current level miss (includes the possibility of misses on successive levels of memory hierarchy) Hit Rate = % of requests that are found in current level cache Miss Rate = 1 - Hit Rate 5 CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB Block Size Tradeoff Conclusions Miss Penalty Block Size Increased Miss Penalty & Miss Rate Average Access Time Block Size Exploits Spatial Locality Fewer blocks: compromises temporal locality Miss Rate Block Size 6
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CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB Types of Cache Misses (1/2) “Three Cs” Model of Misses 1st C: Compulsory Misses • occur when a program is ±rst started • cache does not contain any of that program ʼ s data yet, so misses are bound to occur • can ʼ t be avoided easily, so won ʼ t focus on these 7 CS61C L34 Caches III Wawrzynek, Fall 2007 © UCB Types of Cache Misses (2/2) 2nd C: Con²ict Misses • miss that occurs because two distinct memory addresses map to the same cache location • two blocks (which happen to map to the same location) can keep overwriting each other • big problem in direct-mapped caches • how do we lessen the effect of these?
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L34 - CS61C Machine Structures Lecture 34 - Caches II...

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