L43 - CS61C: Advanced Processors & Course Wrapup CS61C...

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1 CS61C: Advanced Processors CS61C Fall 2007 12/10/2007 Greg Gibeling Outline s Advanced Processors s Sun Niagra s Project Blackbox s The Cell Processor s RAMP Blue s Administrative Details s Course Summary s What you learned (we hope) s The CS Curriculum s Upper Div & Research (1)
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2 Sun Niagra (1) Sun Niagra (2) - Motivation s Observation: s Some apps struggle to reach a CPI == 1. s For throughput on these apps, a large number of single-issue cores is better than a few superscalars.
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3 Sun Niagra (3) - MicroArch s 32 Threads, 8 Cores: s Single-issue, 1.2 GHz s 6-stage pipeline s 4-way multi-threaded s Fast crypto support s Shared Resources: s 3MB on-chip cache s 4 DDR2 interfaces s 32G DRAM, 20 Gb/s s 1 shared FP unit s 1Gb Ethernet ports Sources: Hot Chips, via EE Times, Infoworld. J Schwartz weblog (Sun COO) Die size: 340 mm² in 90 nm. Power: 50-60 W Sun Niagra (4) – T2000 Web server benchmarks used to position the T2000 in the market. Claim: server uses 1/3 the power of competing servers.
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4 Project Blackbox (1) A data center in a 20-ft shipping container. Servers, air-conditioners, power distribution. Project Blackbox (2)
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5 Project Blackbox (3) Project Blackbox (4) Holds 250 T1000 servers. 2000 CPU cores, 8000 threads.
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6 Cell & The PS3 (1)
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7 PowerPC L2 Cache 512 KB Synergistic Processing Units (SPUs) 2X area of Pentium 4 -- 4GHz+ cycle time PowerPC manages the 8 SPUs, also runs serial code. 8 cores using local memory, not traditional caches Cell & The PS3 (3)
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8 s One Synergistic Processing Unit (SPU) s Programmers manage caching explicitly s 256 KB Local Store and 128 128-bit Registers s SPU issues 2 inst/cycle (in order) to 7 execution units s SPU fills Local Store using DMA to DRAM and network Example: Using Cell to Decode HDTV
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9 Advanced Computing s SuperPipelining (SISD) s Run the clock faster s Runs in to physical limits (speed, area, power) s SuperScalar (SISD) s Run multiple instructions at once s Exploit ILP, costs lots of area s Simultaneous Multithreading (MIMD) s Instructions streams can share an OOO engine economically s Static or Dynamic Scheduling s Multi-core (MIMD) s Once ILP runs dry, TLP keeps going s Industry’s billion dollar bet s Vector, MME, SSX, etc. (SIMD) s Great for linear algebra RAMP s RAMP Goals s Build multi-core emulations which run “fast” s Use FPGAs to allow architecture changes and performance measurement (research) s Accelerate the pace of multi-core research s s What RAMP is “Not” Doing s “Not” building multi-core machines s Well, except RAMP Blue s “Not” building FPGA boards s Except for BEE3
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10 BEE2 FPGAs DRAM Compact Flash Card 10GigE ports 10/100 Enet USB DVI/HDMI RAMP Blue (1) - History s V1: 256 cores total s 8 BEE2 modules s 4 user FPGAs * 8 cores per FPGA s 100MHz Xilinx MicroBlaze soft cores running uCLinux. s
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This note was uploaded on 04/09/2008 for the course CS 61A taught by Professor Harvey during the Spring '08 term at University of California, Berkeley.

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L43 - CS61C: Advanced Processors & Course Wrapup CS61C...

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