These faults result in a circuit being accidentally

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diffusion shorts. These faults result in a circuit being accidentally connected—a short circuit. Most short-circuit faults occur in interconnect; often we call these bridging faults (BF). A BF usually results from metal coverage problems that lead to shorts. You may see reference to feedback bridging faults and nonfeedback bridging faults , a useful distinction when trying to predict the results of faults on logic operation. Bridging faults are a frequent problem in CMOS ICs. 14.3.3 Physical Faults Figure 14.11 shows the following examples of physical faults in a logic cell:
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FIGURE 14.11 Defects and physical faults. Many types of defects occur during fabrication. Defects can be of any size and on any layer. Only a few small sample defects are shown here using a typical standard cell as an example. Defect density for a modern CMOS process is of the order of 1 cm –2 or less across a whole wafer. The logic cell shown here is approximately 64 ¥ 32 l 2 , or 250 m m 2 for a l = 0.25 m m process. We would thus have to examine approximately 1 cm –2 /250 m m 2 or 400,000 such logic cells to find a single defect. F1 is a short between m1 lines and connects node n1 to VSS. F2 is an open on the poly layer and disconnects the gate of transistor t1 from the rest of the circuit. F3 is an open on the poly layer and disconnects the gate of transistor t3 from the rest of the circuit. F4 is a short on the poly layer and connects the gate of transistor t4 to the gate of transistor t5. F5 is an open on m1 and disconnects node n4 from the output Z1. F6 is a short on m1 and connects nodes p5 and p6. F7 is a nonfatal defect that causes necking on m1.
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Once we have reduced the large number of physical faults to fewer logical faults, we need a model to predict their effect. The most common model is the stuck-at fault model . 14.3.4 Stuck-at Fault Model The single stuck-at fault ( SSF ) model assumes that there is just one fault in the logic we are testing. We use a single stuck-at fault model because a multiple stuck-at fault model that could handle several faults in the logic at the same time is too complicated to implement. We hope that any multiple faults are caught by single stuck-at fault tests [Agarwal and Fung, 1981;Hughes and McCluskey, 1986]. In practice this seems to be true. There are other fault models. For example, we can assume that faults are located in the transistors using a stuck-on fault and stuck-open fault (or stuck-off fault ). Fault models such as these are more realistic in that they more closely model the actual physical faults. However, in practice the simple SSF model has been found to work—and work well. We shall concentrate on the SSF model. In the SSF model we further assume that the effect of the physical fault (whatever it may be) is to create only two kinds of logical fault. The two types of logical faults or stuck-at faults are: a stuck- at-1 fault (abbreviated to SA1 or [email protected]) and a stuck-at-0 fault ( SA0 or [email protected]). We say that we place
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  • Fall '15
  • prasad
  • Logic gate, NOR gate, fault simulation

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