Register next cycle forwarding or only from the memwb

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register (next-cycle forwarding) or only from the MEM/WB pipeline register (two-cycle forwarding). What is the CPI for each option?
Add x12, x10, x11 IF ID EX MEM WB Add x10, x10, x11 IF ID EX MEM WB NOP Bubble Addi x12, x12, 1 IF ID EX MEM WB CPI = (4+4) / 3 = 8/3 MEM to 2nd Addi x12, x10, 1 IF ID EX MEM WB Add x10, x10, x11 IF ID EX MEM WB Addi x11, x12, 1 IF ID EX MEM WB CPI = (3+4) / 3 = 7/3 EX to 1st and 2nd Add x12, x10, x11 IF ID EX MEM WB NOP Bubble NOP Bubble Add x10, x12, x11 IF ID EX MEM WB Add x12, x12, x10 IF ID EX MEM WB CPI = (5+4) / 3 = 3 6.7 For the given hazard probabilities and pipeline stage latencies, what is the speedup achieved by each type of forwarding (EX/MEM, MEM/WB, for full) as compared to a pipeline that has no forwarding?
6.8 What would be the additional speedup (relative to the fastest processor from 6.7) be if we added “timetravel” forwarding that eliminates all data hazards? Assume that the yet-to-be- invented time-travel circuitry adds 100 ps to the latency of the full-forwarding EX stage.

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