0 r 0 then q q prev s 1 r 1 then q 0 and q 0 r s q q

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= 0, R = 0: then Q = Q prev S = 1, R = 1: then Q = 0 and Q = 0 R S Q Q N1 N2 1 1 R S Q Q N1 N2 0 0 R S Q Q N1 N2 0 0 0 Q prev = 0 Q prev = 1 9
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S R y Q Q = (R+y)’ y = (S+Q)’ 10
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Flip-flop Components S R SR F-F (Set-Reset) Inputs: S, R State: (Q, y) y Q 11
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Id Q y S R Q* y Q** y** Q*** y*** 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 0 1 0 1 2 0 0 1 0 1 0 1 0 1 0 3 0 0 1 1 0 0 0 0 0 0 4 0 1 0 0 0 1 0 1 0 1 5 0 1 0 1 0 1 0 1 0 1 6 0 1 1 0 0 0 1 0 1 0 7 0 1 1 1 0 0 0 0 0 0 8 1 0 0 0 1 0 1 0 1 0 9 1 0 0 1 0 0 0 1 0 1 10 1 0 1 0 1 0 1 0 1 0 11 1 0 1 1 0 0 0 0 0 0 12 1 1 0 0 0 0 1 1 0 0 13 1 1 0 1 0 0 0 1 0 1 14 1 1 1 0 0 0 1 0 1 0 15 1 1 1 1 0 0 0 0 0 0 Q y State Transition SR 10 10 00 11 00 10 SR 11 10 01 11 01 11 01 10 00 10 00 01 00 11 State Diagram 01 12
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CASES: SR=01, (Q,y) = (0,1) SR=10, (Q,y) = (1,0) SR=11, (Q,y) = (0,0) SR = 00 => if (Q,y) = (0,0) or (1,1), the output keeps changing Solutions: 1) SR = (0,0), or 2) SR = (1,1). 0 0 0 1 - 1 1 0 1 - PS inputs 00 01 10 11 State table Q(t+1) SR Characteristic Expression Q(t+1) = S(t)+R’(t)Q(t) NS (next state) Q(t) 13
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SR Latch Analysis S = 0, R = 0: then Q = Q prev and Q = Q prev ( memory! ) S = 1, R = 1: then Q = 0 and Q = 0 ( invalid state: Q ≠ NOT Q ) R S Q Q N1 N2 1 1 0 0 0 0 R S Q Q N1 N2 0 0 1 0 1 0 R S Q Q N1 N2 0 0 0 1 0 1 Q prev = 0 Q prev = 1 14
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SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state ( Q ) Control what value is being stored with S , R inputs Set: Make the output 1 ( S = 1, R = 0, Q = 1 ) Reset: Make the output 0 ( S = 0, R = 1, Q = 0 ) Must do something to avoid invalid state (when S = R = 1) S R Q Q SR Latch Symbol 15
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D Latch
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  • Fall '06
  • Rosing
  • Logic gate, CLK, Flip-flops, Flip-flop, Latch, Qprev

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