Outputs valid at following falling clock edge Reset AB 00 Z 0 X 1 AB 00 Z 0 X 0

Outputs valid at following falling clock edge reset

This preview shows page 37 - 42 out of 48 pages.

Outputs valid at following falling clock edge Reset AB =00 Z =0 X =1 AB =00 Z =0 X =0 AB =00 Z =0 X =1 AB =01 Z =0 X =1 AB =10 Z =1 X =0 AB =1 1 Z =1 X =1 AB =01 Z =0 X Clk A B Z Reset' 100 Chapter 3: Short Review of Sequential Circuits 3-74
Image of page 37
EE271 @ Thuy T. Le SJSU - EE Chapter 3: Short Review of Sequential Circuits 38 Partially completed State Transition Table A B X A+ B+ Z 0 0 0 0 1 0 1 0 0 0 0 1 0 ? ? ? 1 1 1 0 1 0 0 ? ? ? 1 0 1 1 1 1 0 1 0 1 1 ? ? ? K-maps for A +, B +, and Z are then developed from completed Transition Table Chapter 3: Short Review of Sequential Circuits 3-75 Formal Method A+ = B ( A + X ) = AB + BX B+ = J b B' + K b ' B = ( A' XOR X ) B' + XB = AB'X + A'B'X' + BX Z = AX + BX' AB X 00 01 11 10 0 0 0 1 0 1 0 1 1 0 A + AB X 00 01 11 10 0 1 0 0 0 1 0 1 1 1 B + AB X 00 01 11 10 0 0 1 1 0 1 0 0 1 1 Z Can also be built from Transition Table developed by Ad Hoc technique Chapter 3: Short Review of Sequential Circuits 3-76
Image of page 38
EE271 @ Thuy T. Le SJSU - EE Chapter 3: Short Review of Sequential Circuits 39 Some outputs in output boxes as well as state boxes This is intrinsic in Mealy machine implementation Complete Mealy ASM Chart S 0 = 00, S 1 = 01, S 2 = 10, S 3 = 11 S 0 00 X H. Z 01 10 X H. Z H. Z 11 X X 0 1 0 0 1 1 0 1 S 1 S 2 S 3 Chapter 3: Short Review of Sequential Circuits 3-77 Finite State Machine Partitioning Why partition? Mapping FSM onto programmable logic components that: Have limit number of input/output pins Have limited number of product terms or other programmable resources Next states and output functions 10 inputs 7 outputs Partition 1 Partition 2 7 inputs 6 inputs 10 inputs 4 outputs 3 outputs Chapter 3: Short Review of Sequential Circuits 3-78
Image of page 39