Table 6 27 eQEP Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX

Table 6 27 eqep switching characteristics parameter

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Table 6-27. eQEP Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT t d(CNTR)xin Delay time, external clock to counter increment 4t c(SCO) cycles t d(PCS-OUT)QEP Delay time, QEP input edge to position compare sync 6t c(SCO) cycles output Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 139 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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ADCSOCAO or ADCSOCBO t w(ADCSOCL) XNMI , XINT1, XINT2 t w(INT) Interrupt Vector t d(INT) Address bus (internal) TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.10.5 ADC Start-of-Conversion Timing Table 6-28. External ADC Start-of-Conversion Switching Characteristics PARAMETER MIN MAX UNIT t w(ADCSOCL) Pulse duration, ADCSOCxO low 32t c(HCO ) cycles Figure 6-16. ADCSOCAO or ADCSOCBO Timing 6.11 External Interrupt Timing Figure 6-17. External Interrupt Timing Table 6-29. External Interrupt Timing Requirements (1) TEST CONDITIONS MIN MAX UNIT t w(INT) (2) Pulse duration, INT input low/high Synchronous 1t c(SCO) cycles With qualifier 1t c(SCO) + t w(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-13 . (2) This timing is applicable to any GPIO pin configured for ADCSOC functionality. Table 6-30. External Interrupt Switching Characteristics (1) PARAMETER MIN MAX UNIT t d(INT) Delay time, INT low/high to interrupt-vector fetch t w(IQSW) + 12t c(SCO) cycles (1) For an explanation of the input qualifier parameters, see Table 6-13 . 140 Electrical Specifications Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.12 I2C Electrical Specification and Timing Table 6-31. I2C Timing TEST CONDITIONS MIN MAX UNIT f SCL SCL clock frequency I2C clock module frequency is between 400 kHz 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately v il Low level input voltage 0.3 V DDIO V V ih High level input voltage 0.7 V DDIO V V hys Input hysteresis 0.05 V DDIO V V ol Low level output voltage 3-mA sink current 0 0.4 V t LOW Low period of SCL clock I2C clock module frequency is between 1.3 m s 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately t HIGH High period of SCL clock I2C clock module frequency is between 0.6 m s 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately l I Input current with an input voltage –10 10 m A between 0.1 V DDIO and 0.9 V DDIO MAX 6.13 Serial Peripheral Interface (SPI) Timing This section contains both Master Mode and Slave Mode timing data. 6.13.1 Master Mode Timing Table 6-32 lists the master mode timing (clock phase = 0) and Table 6-33 lists the timing (clock phase = 1). Figure 6-18 and Figure 6-19 show the timing waveforms.
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