124 661 General Notes on Timing Parameters 124 662 Test Load Circuit 124 663

124 661 general notes on timing parameters 124 662

This preview shows page 3 - 6 out of 200 pages.

124 6.6.1 General Notes on Timing Parameters ...................................................................... 124 6.6.2 Test Load Circuit .............................................................................................. 124 6.6.3 Device Clock Table ........................................................................................... 125 6.7 Clock Requirements and Characteristics ............................................................................. 126 6.8 Power Sequencing ....................................................................................................... 127 6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 127 6.9 General-Purpose Input/Output (GPIO) ................................................................................ 130 6.9.1 GPIO - Output Timing ........................................................................................ 130 6.9.2 GPIO - Input Timing .......................................................................................... 131 6.9.3 Sampling Window Width for Input Signals ................................................................. 132 6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 133 6.10 Enhanced Control Peripherals ......................................................................................... 138 6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 138 6.10.2 Trip-Zone Input Timing ....................................................................................... 138 6.10.3 Enhanced Capture (eCAP) Timing ......................................................................... 139 6.10.4 Enhanced Quadrature Encoder Pulse (eQEP) Timing ................................................... 139 6.10.5 ADC Start-of-Conversion Timing ............................................................................ 140 6.11 External Interrupt Timing ................................................................................................ 140 6.12 I2C Electrical Specification and Timing ............................................................................... 141 6.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 141 Copyright © 2007–2010, Texas Instruments Incorporated Contents 3
Image of page 3
TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.13.1 Master Mode Timing .......................................................................................... 141 6.13.2 SPI Slave Mode Timing ...................................................................................... 146 6.14 External Interface (XINTF) Timing ..................................................................................... 149 6.14.1 USEREADY = 0 ............................................................................................... 149 6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 150 6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 151 6.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 153 6.14.5 External Interface Read Timing ............................................................................. 154 6.14.6 External Interface Write Timing ............................................................................. 156 6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 158 6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 161 6.14.9 XHOLD and XHOLDA Timing ............................................................................... 164 6.15 On-Chip Analog-to-Digital Converter .................................................................................. 167 6.15.1 ADC Power-Up Control Bit Timing .......................................................................... 168 6.15.2 Definitions ...................................................................................................... 169 6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 170 6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 171 6.15.5 Detailed Descriptions ......................................................................................... 172 6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 173 6.16.1 McBSP Transmit and Receive Timing ...................................................................... 173 6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 176 6.17 Flash Timing .............................................................................................................. 180 6.18 Migrating Between F2833x Devices and F2823x Devices ......................................................... 181 7 Revision H Revision History .............................................................................................. 182 8 Revision G Revision History .............................................................................................. 183 9 Thermal/Mechanical Data .................................................................................................. 186 4 Contents Copyright © 2007–2010, Texas Instruments Incorporated
Image of page 4
TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 List of Figures 2-1 F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View) ...................................................................... 16 2-2 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View) .............................. 17 2-3 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View) ............................. 18 2-4 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View) .............................. 19 2-5 F2833x, F2823x 179-Ball ZHH MicroStar BGA ™(Lower Right Quadrant) (Bottom View) ............................. 20 2-6 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View) ...................................... 21 2-7 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View) .................................... 22 2-8 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View) ...................................... 23 2-9 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View) .................................... 23 3-1 Functional Block Diagram ...................................................................................................... 34 3-2 F28335/F28235 Memory Map .................................................................................................
Image of page 5
Image of page 6

You've reached the end of your free preview.

Want to read all 200 pages?

  • Summer '20
  • Serial Peripheral Interface Bus, Texas Instruments Incorporated, TMS320F28335

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

Stuck? We have tutors online 24/7 who can help you get unstuck.
A+ icon
Ask Expert Tutors You can ask You can ask You can ask (will expire )
Answers in as fast as 15 minutes