lect15-adv-microarchitecture

Under load shadow analogous to squashing recovery in

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under load shadow Analogous to squashing recovery in branch misprediction Simple but high performance penalty Independent instructions are unnecessarily replayed Sched Disp RF Exe Retire  Invalidate & replay  ALL   instructions in the load  shadow LD ADD OR AND BR AND ADD AND BR miss resolved LD AND BR LD ADD OR Cache miss AND BR
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Position-based selective replay Ideal selective recovery replay dependent instructions only Dependence tracking is managed in a matrix form Column: load issue slot, row: pipeline stages merge matices ADD 0 0 0 0 0 0 0 1 OR 0 0 0 0 0 0 0 1 SLL 0 0 0 0 0 0 0 1 AND 0 0 0 0 1 0 0 1 XOR 0 0 0 0 1 0 0 0 LD LD ADD OR XOR AND SLL Integer  pipeline Mem pipeline (width 2) Sched Disp RF Exe Retire ADD 0 0 0 0 0 1 0 0 OR 0 0 0 0 0 1 0 0 XOR 0 0 1 0 0 0 0 0 LD LD OR AND SLL ADD XOR SLL 0 0 0 0 0 1 0 0 AND 0 0 1 0 0 1 0 0 tag / dep info broadcast kill bus broadcast killed killed killed killed Cycle  n Cycle  n+1 Sched Disp RF Exe Retire 1 0 0 1 0 0 1 0 bit merge & shift invalidate if bits match in the last row tagR ReadyR ReadyL tagL = = Kill bus tag bus dependence info bus Cache miss Detected
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Low-complexity scheduling  techniques FIFO (Palacharla, Jouppi, Smith, 1996) Replaces conventional scheduling logic with multiple FIFOs Steering logic puts instructions into different FIFOs considering  dependences A FIFO contains a chain of dependent instructions Only the head instructions are considered for issue
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FIFO (cont’d) Scheduling example
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FIFO (cont’d) Performance Comparable performance to the conventional scheduling Reduced scheduling logic complexity Many related papers on  clustered microarchitecture Can in-order clusters provide high performance? [Zilles  reading]
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Memory Dataflow
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Key Challenge: MLP Tolerate/overlap memory latency Once first miss is encountered, find another  one Na ï ve solution Implement a very large ROB, IQ, LSQ Power/area/delay make this infeasible Build  virtual  instruction window
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Runahead Use poison bits to eliminate miss- dependent  load   program slice Forward load slice processing is a very old  idea Massive Memory Machine   [Garcia-Molina et al. 84] Datascalar  [Burger, Kaxiras, Goodman 97] Runahead proposed by  [Dundas, Mudge 97] Checkpoint state, keep running When miss completes, return to  checkpoint May need runahead cache for store/load  communication
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Waiting Instruction Buffer [Lebeck et al. ISCA 2002] Capture forward load slice in separate  buffer Propagate poison bits to identify slice Relieve pressure on issue queue Reinsert instructions when load completes Very similar to Intel Pentium 4 replay  mechanism But  not publicly known at the time
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