In the xc3000 family they consist of five horizontal

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channels are to gate arrays. In the XC3000 family, they consist of five horizontal and five vertical lines located between the rows and columns of CLBs. At the intersection of vertical and horizontal lines, there is a switch box, also called a switching matrix, as shown in the Fig. 4.8. Twenty admissible interconnect options of a Xilinx XC3000 switch box are depicted in Fig. 4.9. Some signal-restoring buffers are available along some routing resources to restore signal levels due to degradation through the pass transistors inside the switch boxes. Each XC2000 and XC3000 CLB can be directly connected to its neighboring blocks. The X-output of a CLB is directly connected to the B-output of the CLB immediately to its right and the C-input of the CLB to its left. The Y-output is connected to the A- and D- input of the CLB below and above, respectively. Direct interconnect is also provided between the CLBs (along the logic cell boundary) and some IOBs. Direct interconnect typically has less routing delay than general-purpose interconnect and long lines. Long interconnect lines or long lines are available along the vertical and horizontal channels. They bypass the switch boxes and have less skew than general-purpose interconnect. The horizontal long lines in a XC3000 or XC4000 device may be connected to the tri-state buffers that are accessible to CLBs. This feature allows the formation of busses, multiplexers, and wired- AND functions. As in the case of direct interconnections, long lines have the advantage of minimizing delays for high-fanout nets and lowering skew. The interconnect facility in the series 4000 devices is significantly different. In particular, the switch box connections are much simpler.
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Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, Dept. of ECE, KL University 14 Fig. 4.8 Xilinx: General Interconnects Fig. 4.9 Possible switch box connectivities
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Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, Dept. of ECE, KL University 15 4.4.4. The Programming Method In the Xilinx FPGA, both the functional block (CLB) and the interconnects use SRAM cells for keeping the configuration. The RAM cell is shown in Fig. 4.7. It consists of two inverters and a pass transistor. Interconnecting wire segments are made by pass transistors that are controlled by SRAM cells. Since RAM is volatile, a system using Xilinx FPGAs has to be provided with an arrangement to maintain the configuration map of the chip. This volatility makes the chip reprogrammable. At power on, all RAM configurations must be initialized or downloaded typically from an external memory device or from a computer. The configuration bits are shifted into the PIPs or the RAMs inside the CLBs using a built-in-shift register chain. 4.5 Advanced Features of the 4000 Series There are several features in the 4000 series that resulted in an improvement in design flexibility and in device performance: - CLBs can be used as on-chip RAMs - Fast-carry chain - Boundary scan (JTAG) compatibility - Wide decode logic - More global clocks - Faster Placement and routing algorithms - Selected routing resources
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  • Fall '15
  • prasad

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