optimizing pins for block level designs 6 41 overview of interface logic models

Optimizing pins for block level designs 6 41 overview

This preview shows page 453 - 455 out of 455 pages.

optimizing pins for block level designs 6-41 overview of interface logic models 5-2 P packing hard macros 6-39 physical data copying 2-52 physical hierarchy commit 1-10 , 14-1 uncommit 14-11 physical objects, connected to power and ground 14-11 pin assignment analyzing quality of 1-10 , 12-44 connectivity driven 12-10
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Index IN-4 IC Compiler Design Planning User Guide Version D-2010.03-SP4 constraints 12-9 corner calculation 12-4 results, analyzing 12-1 pin constraints assign 12-2 assigning 12-2 pin cutting flow, detecting buses 12-20 pin cutting, in-place optimization 11-7 pin guides creating 12-35 pin overlaps, removing 12-16 placement measuring QoR 6-2 specifying hard macro placement constraints 6-3 placement constraints congestion driven 6-36 effort level 6-36 ignore scan chain connectivity 6-38 incremental placement 6-37 legalizing the placement 6-38 maximum fanout 6-37 optimize pins 6-38 setting on macro cells 6-9 specifying CPUs 6-38 timing driven 6-36 placement options, hierarchical gravity 6-37 plan group-aware routing, detecting buses 12-20 plan groups creating 7-2 defining the shape of 7-3 exclusive 7-2 removing 7-4 uncommit hierarchy 14-1 pre-budget timing analysis 13-3 propagate preroutes 14-1 prototype global routing, running 9-2 pushed up physical objects 14-12 pushed up, physical objects 14-11 Q quick timing model for black boxes command summary 13-12 using Tcl commands to create 4-10 R read_def command 2-50 read_floorplan command 2-52 reading DEF file 2-50 real clock latencies, creating budgets for 13-29 relative location constraints extracting 6-16 removing 6-17 relative placement in virtual flat placement 6-46 S search control options acceptable overflow 3-14 auto routability 3-14 set_fp_placement_strategy -auto_grouping 6-19 -congestion_effort 6-25 -fix_macros 6-22 -honor_mv_cells 6-25 -IO_net_weight 6-24 -legalizer_effort 6-26 -macro_orientation 6-18 -macro_setup_only 6-19 -macros_on_edge 6-20 -plan_group_interface_net_weight 6-24 -sliver_size 6-21 -snap_macros_to_user_grid 6-22 -spread_spare_cells 6-26 -virtual_IPO 6-27 shaping objects 7-18 sliver_size option, using for estimate_fp_area 3-6
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Index IN-5 IC Compiler Design Planning User Guide Version D-2010.03-SP4 sliver_size parameter 3-11 soft macros discarded pins 12-10 no pins created in edge 12-3 properties set in CEL view 14-11 uncommit physical hierarchy 14-1 switching activity, annotating 8-36 T timing budgeting creating real clock latencies 13-29 performing in design planning 13-1 pre-budget timing analysis 13-3 prerequisites 13-2 running 13-6 U update_voltage_area command 6-35 V virtual flat placement strategy, using constraints to control 6-17 voltage areas planning location and shape of 6-30 removing commands remove_voltage_area 6-35 supporting physical boundary scenarios 6-34 updating 6-35
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