# 60 the degenerated stage depicted in fig 783 must

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60. The degenerated stage depicted in Fig. 7.83 must provide a voltage gain of 4 with a power budget of 2 mW while the voltage drop across is equal to 200 mV. If the overdrivevoltage of the transistor must not exceed 300 mV and must consume less than than of the allocated power, design the circuit. Make the same assumptions as those in Problem 57. 61. Design the circuit of Fig. 7.83 for a voltage gain of 5 and a power budget of 6 mW. Assume

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 368 (1) 368 Chap. 7 CMOS Amplifiers M 1 V DD in V I 1 C out V 1 R L 50 = 1.8 V Figure 7.79 M 1 V DD out V in V M 2 V b R S M 1 V DD out V in V M 2 V b R S M M 1 V DD out V in V 2 M 1 V DD out V in V M R 1 R 2 M M 1 V DD out V 2 M in V 3 V b M out V in V M V M 3 V 2 1 b1 b2 V DD (d) (c) (a) (b) (e) (f) 2 Figure 7.80 in V R D M M 1 2 I V DD 1 out V V b X Figure 7.81 the voltage drop across is equal to the overdrive voltage of the transistor and . 62. The circuit shown in Fig. 7.84 must provide a voltage gain of 6, with serving as a low impedance at the frequencies of interest. Assuming a power budget of 2 mW and an input impedance of 20 k , design the circuit such that operates 200 mV away from the triode region. Select the values of and so that their impedance is negligible at 1 MHz. 63. In the circuit of Fig. 7.85, serves as a current source. Design the stage for a voltage
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 369 (1) Sec. 7.6 Chapter Summary 369 M V DD R in V C 1 G C 2 out V R D 1 = 1.8 V Figure 7.82 M 1 V DD = 1.8 V R 1 R 2 C 1 in V R D out V R S Figure 7.83 C M 1 V DD = 1.8 V R 1 C 1 in V R D out V R S S Figure 7.84 V DD M 1 M 2 out V in V V b = 1.8 V Figure 7.85 gain of 20 and a power budget of 2 mW. Assume for both transistors and the maximum allowable level at the output is 1.5 V (i.e., must remain in saturation if V). 64. Consider the circuit shown in Fig. 7.86, where is very large and V . (a) Calculate the voltage gain. (b) Design the circuit for a voltage gain of 15 and a power budget of 3 mW. Assume and the dc level of the output must be equal to . 65. The CS stage of Fig. 7.87 incorporates a degenerated PMOS current source. The degener- ation must raise the output impedance of the current source to about such that the voltage gain remains nearly equal to the intrinsic gain of . Assume for both

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 370 (1) 370 Chap. 7 CMOS Amplifiers V DD M 1 M 2 out V in V R G C B = 1.8 V Figure 7.86 V DD M 1 M 2 out V in V V b R S = 1.8 V Figure 7.87 transistors and a power budget of 2 mW. (a) If V, determine the values of and so that the impedance seen looking into the drain of is equal to . (b) Determine to achieve a voltage gain of 30. 66. Assuming a power budget of 1 mW and an overdrive of 200 mV for , design the circuit shown in Fig. 7.88 for a voltage gain of 4.
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