The first two delays specify the simulation time elapsed in a transition to the

The first two delays specify the simulation time

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The first two delays specify the simulation time elapsed in a transition to the 1 and 0 logic values in the driven state The third delay : For the other net types shows the time that elapses in a transition to the z logic state For the trireg net type specifies the charge decay time The charge decay process ends under one of the following two conditions: 1. The specified number of time units elapse and the trireg makes a transition from 1 or 0 to x 2. One of the drivers turn on and propagate a 1, 0 or x into it
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Decay Example
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Decay Example (cont.)
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Charge Sharing Example module triregChargeSharing; reg a, b, c; wire x; trireg (large) y; // declaration with large strength trireg (small) z; / / declaration with small strength not not1 (x, a); nmos nmos1 (y, x, b); nmos nmos2 (z, y, c); // nmos that drives the trireg
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Charge Sharing Example (cont.) initial begin a = 0; b = 1; c = 1; #10 c = 0; a = 1; #10 c = 1; b = 0; end endmodule
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References The Verilog® Hardware Description Language by Donald Thomas and Philip Moorby (2008) Digital System Designs and Practices: Using Verilog HDL and FPGAs by Ming-Bo Lin (2008) Verilog HDL (2nd Edition) by Samir Palnitkar (2003)
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