2 process dependent clock skew in cmos vlsi ni non

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2 Process Dependent Clock Skew in CMOS VLSI NI (Non-inverting) I (inverting) D (Decoded/Clock Gated) Multiple clock grids Power down when not used Example of process spread and delay variation Process NFET PFET delay ratio delay ratio 88ps 0.556 201ps 0.62 158ps 1.0 325ps 1.0 273ps 1.73 530ps 1.63 High current (H) Nom. current (M) Low. current (L) How to account for skew with process spread? Timing waveforms Design carried out assuming nominal parameters Consider what happens when same circuit is processed by (fastN-fastP) high current process Delay for fastN and fastP TA changes by a factor f N >1 –T A ( H ) = T A ( 1 / f N ), 1/f N
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3 Conditions for zero skew (1) Skew=T I (H)-T NI (H)=0 if Case (1) f N =f P T 2 =T B or f N =f P Conditions for zero skew (2) Case (2) –T B =T 2 (pull down delays) –T A +T C =T 1 (pull-up delays) Sum of pull down delays of 1 st chain = sum of pull- down delays of 2 nd logic chain Sum of pull up delays of 1 st chain = sum of pull-up delays of 2 nd logic chain
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