# In this case the input is brought into an inverting

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minimum impact on the signal frequency response. In this case, the input is brought into an inverting gain resistor with the DC adjustment and additional current summed into the inverting node. The resistor values setting this offset adjust- ment are much larger than the signal path resistors. This will insure that this adjustment has minimal impact on the loop gain and hence, the frequency response. FIGURE 8. DC-Coupled, Inverting Gain of –40, with Offset Adjustment. R F 2k ± 250mV Output Adjustment = – = –40 Supply Decoupling Not Shown 5k 5k 95.3 0.1 µ F R G 50 V I 20k 10k 0.1 µ F –5V +5V OPA687 +5V –5V V O V O V I R F R G

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15 OPA687 SBOS065A DISABLE OPERATION The OPA687 provides an optional disable feature that may be used to reduce system power. If the DIS control pin is left unconnected, the OPA687 will operate normally. To dis- able, the control pin must be asserted low. Figure 9 shows a simplified internal circuit for the disable control feature. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As an absolute worst-case example, compute the maximum T J using an OPA687N (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient tem- perature of +85 ° C and driving a grounded 100 load. P D = 10V (20.5mA) + 5 2 /(4 • (100 || 789 )) = 275mW Maximum T J = +85 ° C + (0.28W • 150 ° C/W) = 127 ° C All actual applications will operate at a lower junction temperature than the 127 ° C computed above. Compute your actual output stage power to get an accurate estimate of maximum junction temperature, or use the results shown here as an absolute maximum. BOARD LAYOUT Achieving optimum performance with a high frequency amplifier like the OPA687 requires careful attention to board layout parasitics and external component types. Rec- ommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1 µ F decoupling capaci- tors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2 µ F to 6.8 µ F) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board.
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