d 3 points Assume the memory access latency is 10 cycles and the cache

D 3 points assume the memory access latency is 10

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From your solution in part (b) above, what is the hit rate of the cache? (d) [3 points]Assume the memory access latency is 10 cycles and the cache, mentioned in this problem, has an access latency of 3 cycles. Also assume the hit rate you calculated in part (c) above. Did this system benefit from having a cache? Justify
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3.int array1[M][N]; int array2[N][M]; int copy(int i, int j) { array1[i][j] = array2[j][i]; } Suppose the above code generates the following assembly code (assume array2 and array1 are the base addresses of the corresponding arrays): copy: movl %rdi, %ecx movl %rsi, %ebx leal (%ecx,%ecx,8), %edx sall $2, %edx movl %ebx, %eax sall $4, %eax subl %ebx, %eax sall $2, %eax movl array2(%eax,%ecx,4), %eax movl %eax, array1(%edx,%ebx,4) ret What are the values of M and N (2 points)? Show how did you reach your answer (2 points)
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4. [2 points] Consider the two C functions fun1 and fun2. Which of these two functions compiled into the assembly code shown? int fun1(int a, int b) movl %rdi, %edx{ movl %rsi, %eaxif (a < b) cmpl %eax, %edx return a; jge .L9else movl %edx, %eaxreturn b; .L9:} int fun2(int a, int b) { if (b < a ) return b; else return a; }
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