When the gate is at a high voltage positive charge on

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nMOS Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Slide 18 n+ p Gate Source Drain bulk Si SiO 2 Polysilicon n+ D 1 S
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pMOS Transistor Similar, but doping and voltages reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Slide 19 SiO 2 n Gate Source Drain bulk Si Polysilicon p+ p+
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Power Supply Voltage GND(ground) = 0 V In 1980’s, VDD (power)= 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … Slide 20
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Lower VDD saves power 21
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Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path(current) from source to drain Slide 22 g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
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