EEL6323-S11-HLec020-Sequencing-2spp

Reset reset reset synchronous reset asynchronous

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reset reset reset Synchronous Reset Asynchronous Reset Symbol Flop DQ Latch reset reset  Q reset Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches Flip-Flops clk 1 2 p clk clk p p 1 1 2 2-Phase Transparent Latches Pulsed Latches Combinational Logic Combinational Logic Combinational Logic Combinational Logic T c T c /2 t nonoverlap t nonoverlap t pw Half-Cycle 1 Half-Cycle 1
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6 Timing Diagrams Flop A Y t pd Combinational Logic AY DQ clk clk D Q Latch clk clk D Q t cd t setup t hold t ccq t pcq t ccq t setup t hold t pcq t pdq t cdq t hold t setup t pcq t pdq t ccq t pcq t cd t pd Contamination and Propagation Delays Max-Delay: Flip-Flops F1 F2 clk clk clk Combinational Logic T c Q1 D2 Q1 D2 t pd t setup t pcq
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7 EX T adder =590ps T result_mux =60ps T middle_bypass_mux =80ps T late_bypass_mux =70ps 2mm wire=100ps each T setup =62ps T hold =-10ps T pcq =90ps T pd =1000ps T C >1000+62+90ps Max Delay: 2-Phase Latches T c Q1 L1 1 2 L2 L3 1 1 2 Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D3 D1 t pd1 t pdq1 t pd2 t pdq2
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8 Max Delay: Pulsed Latches T c Q1 Q2 D1 D2 Q1 D2 D1 p p p Combinational Logic L1 L2 t pw (a) t pw > t setup Q1 D2 (b) t pw < t setup T c t pd t pdq t pcq t pd t setup Min-Delay: Flip-Flops CL clk Q1 D2 F1 clk Q1 F2 clk D2 t cd t hold t ccq
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  • Fall '09
  • Guan
  • Logic gate, D1, CLK, tccq tpcq

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