EEL6323-S11-HLec08-Circuit-SimsModels-2spp

Is effectively doubled when wait long enough for

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Unformatted text preview: is effectively doubled when wait long enough for drain to completely switch (Miller effect) – Example: circuit for determining the effective gate capacitance of X1 for power estimation • Apply voltage step and integrate the current into X1 Vdd dt t i power C in g ) ( ) ( Integrated over entire transition (delay is 50% point only) 6 Parasitic Capacitance • Parasitic Capacitance Extraction – Parasitic capacitance associated with drain or source includes gate-to-diffusion overlap cap (C gol ) and area and perimeter cap C jb and C jbsw Effective Resistance • According to RC delay model, Unit transistor has gate cap C, parasitic cap Cd, resistance Rn (for nMOS) and resistance Rp (for pMOS) • Find rising falling delays of fanout-of-h with 2:1 P/N ratio using Figure below 7 Effective Resistance w/o Cd • Remove dependence on parasitic capacitance Cd • Calculate delay for h=3 and h=4, and subtract C R C C R C C R t C R C C R C C R t n d n d n pdf p d p d p pdr 2 3 3 3 3 3 4 3 2 3 3 3 3 2 3 4 3 2 Summary • Simple simulations to extract R, Cg, Cd • More in Ch5...
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  • Fall '09
  • Guan
  • Inductor, Threshold voltage, Parasitic capacitance, gate capacitance

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