not perform computation on the radio data itself but serves as a relay to the

Not perform computation on the radio data itself but

This preview shows page 6 - 8 out of 10 pages.

not perform computation on the radio data itself but serves as a relay to the datapath. Many commodity microcontrollers include several low- power modes that put the processor to sleep ; the amount of time it takes to go to sleep and wake up is very important. Asynchronous circuits by nature do not require a clock. The authors argue SNAP can fall asleep in nanoseconds because all circuit switching stops once the event queue is empty. This technique is effective for 180 nm technolo- gies where leakage current is small. However, as leakage current increases, systems based on SNAP will need to incorporate low leakage techniques. BitSNAP, the latest version of the SNAP architecture, replaces the parallel datapath in SNAP/LE with a bit-serial datapath that takes more time to compute operations but consumes 70% less energy than SNAP/LE. 5 BitSNAP also includes dynamic significance compression to selectively adjust the number of iterations run on the serial datapath depending on number of significant bits in the operands. Serial datapaths are interesting from a power perspective because they have fewer transistors than parallel datapaths and result in a smaller effective width on the leakage cur- rent path. 4.5. Charm—Network Stack Acceleration The Charm Protocol processor out of the Berkeley Wire- less Research Center realizes a large portion of a cus- tom radio stack in hardware. 19 The custom radio stack roughly corresponds to the OSI reference model. Charm implements the application, network, data link, and digital baseband portion of the OSI radio stack as well as JTAG Oscillator Voltage converter 64 kB memory 256 B register file dw8051 microcontroller applications &radio Power control bus ADC Charm digital protocol processing chip OOK Tx/Rx Interface (SPI, I2C, GPIO) Serial (Console) Location Neighbor Power manager 1 kB packet queues Data link layer (DLL) Baseband External radio test port Fig. 4. The charm protocol processor microarchitecture. Reprinted with permission from [19], M. Sheets et al., A power-managed protocol pro- cessor for wireless sensor networks. VLSI , June (2006) . © 2006. 6 J. Low Power Electronics 4, 1–10, 2008
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Hempstead et al. Survey of Hardware Systems for Wireless Sensor Networks hardware for a localization subsystem. Figure 4 presents the Charm microarchitecture, which includes blocks for each of the major subsystems. One unique feature of Charm is its power management infrastructure. The authors recognized that leakage current is a significant portion of total power consumption. Charm contains a separate power domain for each of the protocol stack subsystems. Instead of completely gating the power domain Charm includes switches to select between two different supply voltages VDD hi and VDD low . VDD low is set to the lowest voltage that maintains state in the logic.
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  • Fall '18
  • Mr. Bhullar
  • Sensor node, Wireless sensor network

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