Dynamically sensitized a path is dynamically

Dynamically Sensitized
•
A path is dynamically sensitizable if at least one of the side
inputs along a path switches the value and that allows signal
propagation along the path.
Example: In_2-w1-w2-w3-w4-Out_0 is a false path
under static sensitization
Chapter 3: Timing Analysis and Optimization 42
w0
w1 w2
w3
w4
In_2
In_1
In_0
Out_0
G1 G2
G3 G4
G5
G6
1  0
X  0  1
X  X  0  w4 1  0

EE271 @ Thuy T. Le SJSU - EE
Chapter 3: Timing Analysis and Optimization 22
Chapter 3: Timing Analysis and Optimization 43
Dynamic/Simulation Timing Analysis
DTA can also have problems: If DTA is
wrong then:
•
Reduce gate delays result in increasing
delay estimates
•
This is not acceptable since gate delays
we used are upper-bounds
Chapter 3: Timing Analysis and Optimization 44
output out;
input in0, in1;
wire w1, w2, w3, w4;
buf #2 (w1, in0);
buf #1 (w2, in1);
buf #4 (w3, in1);
//buf #2 (w3, in1);
and #1 (w4, w1, w2);
and #1 (out, w4, w3);
endmodule

EE271 @ Thuy T. Le SJSU - EE
Chapter 3: Timing Analysis and Optimization 23
Chapter 3: Timing Analysis and Optimization 45
module DTA1_TB();
reg in0, in1;
wire out;
initial
begin
in0 = 1'b1; in1 = 1'b0;
#10 in0 = 1'b0; in1 = 1'b1;
#20 $finish;
end
DTA1 M1 (out, in0, in1);
endmodule
T1 0 T2 Tdelta
Name
0 10 20 3
Default
in0
in1
w1
w2
w3
w4
out
So, we want Monotone Speedup (or
Robustness ) which means:
•
Longest delay estimated for
reduced-gate-delay circuit 
longest delay estimated for
original circuit (max. gate delays)
•
Timing simulation doesn’t meet
this property
Chapter 3: Timing Analysis and Optimization 46
T1 T2 Tdelta
Name
0 10 20
Default
in0
in1
w1
w2
w3
w4
out
output out;
input in0, in1;
wire w1, w2, w3, w4;
buf #2 (w1, in0);
buf #1 (w2, in1);
//buf #4 (w3, in1);
buf #2 (w3, in1);
and #1 (w4, w1, w2);
and #1 (out, w4, w3);
endmodule

EE271 @ Thuy T. Le SJSU - EE
Chapter 3: Timing Analysis and Optimization 24
On-Chip Variation (OCV)

In case of thin technologies (90nm and below), parameters can
vary due to
 Manufacturing process called on-chip variation (OCV)
 Operating conditions such as temperature, supply voltage, etc...

OCV is defined as variations on the same chip such as
 Metal layer thickness and resistivity
 Line width and spacing
 Dielectric thickness and constant, etc...

On-chip variations are due to
 Purely random: Not depend on the place of cell in the die or of a device
within a cell ( intra-die/intra-cell ) or not depend on which chip (die)
among many chips from one wafer or many wafers ( inter-die )
 Systematic/Deterministic: Variation are caused by the structure of a
particular gate, its locations, and topological environment
Chapter 3: Timing Analysis and Optimization 47

For consideration of variations’ impact, Statistical Static
Timing Analysis (SSTA) tools must be used

Process variations sources and types:
 Lithography Induced Variations
 Etch Induced Variations
 Random Dopant Fluctuations
 Interconnect Variations
 Non-Linear Resistance
 Metal Mismatch, etc...