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6 the number of clock cycles required for an 8257 to

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6. The number of clock cycles required for an 8257 to complete a transfer isa) 2b) 4c) 8d) none of the mentionedView AnswerAnswer: bExplanation: The 8257 uses four clock cycles to complete a transfer.7. In 8257, if each device connected to a channel is assigned to a fixed prioritythen it is said to be ina) rotating priority schemeb) fixed priority schemec) rotating priority and fixed priority schemed) none of the mentionedView AnswerAnswer: bExplanation: In this scheme, the DRQ3 has the lowest priority followed by DRQ2 andDRQ1. The DRQ0 has the highest priority.8. The priority of the channels varies frequently ina) rotating priority schemeb) fixed priority schemec) rotating priority and fixed priority schemed) none of the mentionedView AnswerAnswer: aExplanation: In this scheme, the priorities assigned to the channels are not fixed.9. The register of 8257 that can only be written in isa) DMA address registerb) Terminal count registerc) Mode set registerd) Status registerView AnswerAnswer: cExplanation: The selected register may be read or written depending on theinstruction executed by the CPU. But only write operation can be performed on themode set register.10. The operation that can be performed on the status register isa) write operationb) read operationc) read and write operationsd) none of the mentionedView AnswerAnswer: bExplanation: The status register can only be read.
Microprocessors Questions and Answers – Programmable DMA Interface 8237 -1« PrevNext »This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on“Programmable DMA Interface 8237 -1”.1. The block of 8237 that decodes the various commands given to the 8237 by the CPUisa) timing and control blockb) program command control blockc) priority blockd) none of the mentionedView AnswerAnswer: bExplanation: The program control block decodes various commands given to the 8237by the CPU before servicing a DMA request.2. The priority between the DMA channels requesting the services can be resolved bya) timing and control blockb) program command control blockc) priority blockd) none of the mentionedView AnswerAnswer: cExplanation: The priority encoder block resolves the priority between the DMAchannels requesting the services.3. The register that holds the current memory address isa) current word registerb) current address registerc) base address registerd) command registerView AnswerAnswer: bExplanation: The current address register holds the current memory address. Thecurrent address register is accessed during the DMA transfer.4. The register that holds the data byte transfers to be carried out isa) current word registerb) current address registerc) base address registerd) command registerView AnswerAnswer: aExplanation: The current word register is a 16-bit register that holds the datatransfers. The word count is decremented after each transfer, and the new value isstored again in the register.

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Term
Fall
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Tags
Microprocessor, Central processing unit, X86, Intel 8086

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