At the beginning of the next instruction cycle the instruction that is read

At the beginning of the next instruction cycle the

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- At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1. - At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine - The instruction that returns the control to the original program is "indirect BUN 0" Store return address R =1 =0 in location 0 M[0] PC Branch to location 1 PC 1 IEN 0 R 0 Interrupt cycle Instruction cycle Fetch and decode instructions IEN FGI FGO Execute instructions R 1 =1 =1 =1 =0 =0 =0 INPR Input register - 8 bits OUTR Output register - 8 bits FGI Input flag - 1 bit FGO Output flag - 1 bit IEN Interrupt enable - 1 bit
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Basic Computer Orgsnization and Design 44 CSE 211 Register Transfer Operations in Interrupt Cycle Register Transfer Statements for Interrupt Cycle - R F/F 1 if IEN (FGI + FGO)T 0 T 1 T 2 T 0 T 1 T 2 (IEN)(FGI + FGO): R 1 - The fetch and decode phases of the instruction cycle must be modified Replace T 0 , T 1 , T 2 with R'T 0 , R'T 1 , R'T 2 - The interrupt cycle : RT 0 : AR 0, TR PC RT 1 : M[AR] TR, PC 0 RT 2 : PC PC + 1, IEN 0, R 0, SC 0 After interrupt cycle 0 BUN 1120 0 1 PC = 256 255 1 BUN 0 Before interrupt Main Program 1120 I/O Program 0 BUN 1120 0 PC = 1 256 255 1 BUN 0 Memory Main Program 1120 I/O Program 256
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Basic Computer Organization and Design 45 CSE 211 Complete Computer Description =1 (I/O) =0 (Register) =1(Indir) =0(Dir) start SC 0, IEN 0, R 0 R AR PC R’T 0 IR M[AR], PC PC + 1 R’T 1 AR IR(0~11), I IR(15) D 0 ...D 7 Decode IR(12 ~ 14) R’T 2 AR 0, TR PC RT 0 M[AR] TR, PC 0 RT 1 PC PC + 1, IEN 0 R 0, SC 0 RT 2 D 7 I I Execute I/O Instruction Execute RR Instruction AR <- M[AR] Idle D 7 IT 3 D 7 I’T 3 D 7 ’IT3 D 7 ’I’T3 Execute MR Instruction =0(Instruction =1(Interrupt Cycle) Cycle) =1(Register or I/O) =0(Memory Ref) D 7 ’T4 INPR Input register - 8 bits OUTR Output register - 8 bits FGI Input flag - 1 bit FGO Output flag - 1 bit IEN Interrupt enable - 1 bit
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Basic Computer Organization and Design 46 CSE 211 Complete Computer Design Fetch Decode Indirect Interrupt Memory-Reference AND ADD LDA STA BUN BSA ISZ R T 0 : R T 1 : R T 2 : D 7 IT 3 : RT 0 : RT 1 : RT 2 : D 0 T 4 : D 0 T 5 : D 1 T 4 : D 1 T 5 : D 2 T 4 : D 2 T 5 : D 3 T 4 : D 4 T 4 : D 5 T 4 : D 5 T 5 : D 6 T 4 : D 6 T 5 : D 6 T 6 : AR PC IR M[AR], PC PC + 1 D0, ..., D7 Decode IR(12 ~ 14), AR IR(0 ~ 11), I IR(15) AR M[AR] R 1 AR 0, TR PC M[AR] TR, PC 0 PC PC + 1, IEN 0, R 0, SC 0 DR M[AR] AC AC DR, SC 0 DR M[AR] AC AC + DR, E C out , SC 0 DR M[AR] AC DR, SC 0 M[AR] AC, SC 0 PC AR, SC 0 M[AR] PC, AR AR + 1 PC AR, SC 0 DR M[AR] DR DR + 1 M[AR] DR, if(DR=0) then (PC PC + 1), SC 0
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Basic Computer Organization and Design 47 CSE 211 Complete Computer Design Register-Reference CLA CLE CMA CME CIR CIL INC SPA SNA SZA SZE HLT Input-Output INP OUT SKI SKO ION IOF D 7 I T 3 = r IR(i) = B i r: rB 11 : rB 10 : rB 9 : rB 8 : rB 7 : rB 6 : rB 5 : rB 4 : rB 3 : rB 2 : rB 1 : rB 0 : D 7 IT 3 = p IR(i) = B i p: pB 11 : pB 10 : pB 9 : pB 8 : pB 7 : pB 6 : (Common to all register-reference instr) (i = 0,1,2, ..., 11) SC 0
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