Accordingly the CPU should be momentarily prevented from accessing main memory

Accordingly the cpu should be momentarily prevented

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Accordingly, the CPU should be momentarily prevented from accessing main memory when the DMA controller seizes the memory bus. However, if the CPU is still allowed to access data in its primary and secondary caches, a coherency issue may be created if both the CPU and the DMA controller update the same memory locations. 1.21 Some computer systems do not provide a privileged mode of operation in hardware. Is it possible to construct a secure operating system for these computer systems? Give arguments both that it is and that it is not possible. Answer: An operating system for a machine of this type would need to remain in control (or monitor mode) at all times. This could be accomplished by two methods: a. Software interpretation of all user programs (like some BASIC, Java, and LISP systems, for example). The software interpreter would provide, in software, what the hardware does not provide. b. Require meant that all programs be written in high-level languages so that all object code is compiler-produced. The compiler would generate (either in-line or by function calls) the protection checks that the hardware is missing. 1.22 Many SMP systems have different levels of caches; one level is local to each processing core, and another level is shared among all processing cores. Why are caching systems designed this way? Answer: Because each processing core have to have high access time so it need to be very fast but if we use the same level of cache among all processing cores it will be very expensive and it need less access time compare with first level so we design the caching system like this. .
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1.24 Discuss, with examples, how the problem of maintaining coherence of cached data manifests itself in the following processing environments: a. Single-processor systems b. Multiprocessor systems c. Distributed systems Answer: a. Any memory location updated by the processor [think of a store instruction] will first be updated in cache, and later in memory; how much later depends on the cache design [write-back or write-through, if you already know about that]. In a single-processor system, this is a consistency problem, not a coherence problem. b. In a multiprocessor system, two processors might have loaded the same value from memory, and it would be placed in separate caches, one for each processor. If one processor updates the value that should be communicated to the other processor, or to the other processor's cache, depending on how you want to design the caches [to maintain coherence]. You could invalidate the second copy in cache, or update it. The system bus is involved with this operation. Eventually, the memory is updated, as in a single- processor system [to maintain consistency] c. In distributed systems, nothing about cache or memory is shared, but the file system might be shared. If so, the same problems arise by caching files in main memory. The network substitutes for the system bus.
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  • Spring '14
  • DavidW.Mutschler
  • Central processing unit, CPU cache

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