Figure 6 25 Example Read With Synchronous XREADY Access XTIMING register

Figure 6 25 example read with synchronous xready

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Figure 6-25. Example Read With Synchronous XREADY Access XTIMING register parameters used for this example : XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 1 3 1 1 0 N/A (1) N/A (1) N/A (1) 0 = XREADY (Synch) (1) N/A = “Don’t care” for this example Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 159 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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t su(XD)XRD Lead Active Trail DIN t d(XCOH-XZCSL) t d(XCOH-XA) t d(XCOHL-XRDL) t d(XCOHL-XZCSH) t d(XCOHL-XRDH) WS (Async) XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XZCS0, XZCS6 , XZCS7 XA[0:19] XRD XWE0 , XWE1 (D) XR/W XD[0:31], XD[0:15] XREADY(Asynch) t su(XRDYasynchL)XCOHL t a(XRD) t a(A) t h(XRDYasynchL) t h(XD)XRD t h(XRDYasynchH)XZCSH = Don’t care. Signal can be high or low during this time. Legend: (A) (B) (C) t su(XRDYasynchH)XCOHL (E) (F) t e(XRDYasynchH) TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals will transition to their inactive state. C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high. This includes alignment cycles. D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0. E. For each sample, setup time from the beginning of the access can be calculated as: E = (XRDLEAD + XRDACTIVE -3 +n) t c(XTIM) – t su(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) t c(XTIM) Figure 6-26. Example Read With Asynchronous XREADY Access XTIMING register parameters used for this example : XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 1 3 1 1 0 N/A (1) N/A (1) N/A (1) 1 = XREADY (Async) (1) N/A = “Don’t care” for this example 160 Electrical Specifications Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.14.8 External Interface Ready-on-Write Timing With One External Wait State Table 6-45. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) PARAMETER MIN MAX UNIT t d(XCOH-XZCSL) Delay time, XCLKOUT high to zone chip-select active low 1 ns t d(XCOHL-XZCSH) Delay time, XCLKOUT high or low to zone chip-select inactive high – 1 0.5 ns t d(XCOH-XA) Delay time, XCLKOUT high to address valid 1.5 ns t d(XCOHL-XWEL) Delay time, XCLKOUT high/low to XWE0, XWE1 low (1) 2 ns t d(XCOHL-XWEH) Delay time, XCLKOUT high/low to XWE0, XWE1 high (1) 2 ns t d(XCOH-XRNWL) Delay time, XCLKOUT high to XR/W low 1 ns t d(XCOHL-XRNWH) Delay time, XCLKOUT high/low to XR/W high – 1 0.5 ns t en(XD)XWEL Enable time, data bus driven from XWE0, XWE1 low (1) 0 ns t d(XWEL-XD)
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