GPBTOGGLE QUALPRD0 1 0 GPIO32 IO SDAA IOC 1 EPWMSYNCI I ADCSOCAO O 1 3 2 GPIO33

Gpbtoggle qualprd0 1 0 gpio32 io sdaa ioc 1 epwmsynci

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GPBTOGGLE QUALPRD0 0 1, 0 GPIO32 (I/O) SDAA (I/OC) (1) EPWMSYNCI (I) ADCSOCAO (O) 1 3, 2 GPIO33 (I/O) SCLA (I/OC) (1) EPWMSYNCO (O) ADCSOCBO (O) 2 5, 4 GPIO34 (I/O) ECAP1 (I/O) XREADY (I) 3 7, 6 GPIO35 (I/O) SCITXDA (O) XR/W (O) 4 9, 8 GPIO36 (I/O) SCIRXDA (I) XZCS0 (O) 5 11, 10 GPIO37 (I/O) ECAP2 (I/O) XZCS7 (O) 6 13, 12 GPIO38 (I/O) XWE0 (O) 7 15, 14 GPIO39 (I/O) XA16 (O) QUALPRD1 8 17, 16 GPIO40 (I/O) XA0/XWE1 (O) 9 19, 18 GPIO41 (I/O) XA1 (O) 10 21, 20 GPIO42 (I/O) XA2 (O) Reserved 11 23, 22 GPIO43 (I/O) XA3 (O) 12 25, 24 GPIO44 (I/O) XA4 (O) 13 27, 26 GPIO45 (I/O) XA5 (O) 14 29, 28 GPIO46 (I/O) XA6 (O) 15 31, 30 GPIO47 (I/O) XA7 (O) GPBMUX2 GPBMUX2 = 0, 0 GPBMUX2 = 0, 1 GPBMUX2 = 1, 0 GPBMUX2 = 1, 1 GPBQSEL2 QUALPRD2 16 1, 0 GPIO48 (I/O) ECAP5 (I/O) XD31 (I/O) 17 3, 2 GPIO49 (I/O) ECAP6 (I/O) XD30 (I/O) 18 5, 4 GPIO50 (I/O) EQEP1A (I) XD29 (I/O) 19 7, 6 GPIO51 (I/O) EQEP1B (I) XD28 (I/O) 20 9, 8 GPIO52 (I/O) EQEP1S (I/O) XD27 (I/O) 21 11, 10 GPIO53 (I/O) EQEP1I (I/O) XD26 (I/O) 22 13, 12 GPIO54 (I/O) SPISIMOA (I/O) XD25 (I/O) 23 15, 14 GPIO55 (I/O) SPISOMIA (I/O) XD24 (I/O) QUALPRD3 24 17, 16 GPIO56 (I/O) SPICLKA (I/O) XD23 (I/O) 25 19, 18 GPIO57 (I/O) SPISTEA (I/O) XD22 (I/O) 26 21, 20 GPIO58 (I/O) MCLKRA (I/O) XD21 (I/O) 27 23, 22 GPIO59 (I/O) MFSRA (I/O) XD20 (I/O) 28 25, 24 GPIO60 (I/O) MCLKRB (I/O) XD19 (I/O) 29 27, 26 GPIO61 (I/O) MFSRB (I/O) XD18 (I/O) 30 29, 28 GPIO62 (I/O) SCIRXDC (I) XD17 (I/O) 31 31, 30 GPIO63 (I/O) SCITXDC (O) XD16 (I/O) (1) Open drain 104 Peripherals Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 Table 4-18. GPIO-C Mux Peripheral Selection Matrix REGISTER BITS PERIPHERAL SELECTION GPCDIR GPCDAT GPIOx or PER1 PER2 or PER3 GPCSET GPCMUX1 GPCMUX1 = 0, 0 or 0, 1 GPCMUX1 = 1, 0 or 1, 1 GPCCLR GPCTOGGLE no qual 0 1, 0 GPIO64 (I/O) XD15 (I/O) 1 3, 2 GPIO65 (I/O) XD14 (I/O) 2 5, 4 GPIO66 (I/O) XD13 (I/O) 3 7, 6 GPIO67 (I/O) XD12 (I/O) 4 9, 8 GPIO68 (I/O) XD11 (I/O) 5 11, 10 GPIO69 (I/O) XD10 (I/O) 6 13, 12 GPIO70 (I/O) XD9 (I/O) 7 15, 14 GPIO71 (I/O) XD8 (I/O) no qual 8 17, 16 GPIO72 (I/O) XD7 (I/O) 9 19, 18 GPIO73 (I/O) XD6 (I/O) 10 21, 20 GPIO74 (I/O) XD5 (I/O) 11 23, 22 GPIO75 (I/O) XD4 (I/O) 12 25, 24 GPIO76 (I/O) XD3 (I/O) 13 27, 26 GPIO77 (I/O) XD2 (I/O) 14 29, 28 GPIO78 (I/O) XD1 (I/O) 15 31, 30 GPIO79 (I/O) XD0 (I/O) GPCMUX2 GPCMUX2 = 0, 0 or 0, 1 GPCMUX2 = 1, 0 or 1, 1 no qual 16 1, 0 GPIO80 (I/O) XA8 (O) 17 3, 2 GPIO81 (I/O) XA9 (O) 18 5, 4 GPIO82 (I/O) XA10 (O) 19 7, 6 GPIO83 (I/O) XA11 (O) 20 9, 8 GPIO84 (I/O) XA12 (O) 21 11, 10 GPIO85 (I/O) XA13 (O) 22 13, 12 GPIO86 (I/O) XA14 (O) 23 15, 14 GPIO87 (I/O) XA15 (O) Copyright © 2007–2010, Texas Instruments Incorporated Peripherals 105 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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GPyCTRL Reg SYNC SYSCLKOUT Qualification Input Signal Qualified by 3 or 6 Samples GPIOx Time Between Samples GPxQSEL Number of Samples TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
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