Data incoherency data may be captured late causing

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Data Incoherency:Data may be captured late, causing several coherent signals to be in different states.What is the probability of metastability?Let us define:Twan error window (setup+hold)around the clock cyclefclock frequencyfDFrequency of data changeNow assume that a data (D) change can come anywhere in the clock cycle relative to the capture clock, so:()DmetawRateffT=Assume: ()D61GHz0.120ps2 10metasecwfffTRate====
51©Adam Teman, 2018By cascading two or more flip flops, we create a simple synchronizer.The signal has one (or more) clock cycles to stabilize.However, there is a probability that the signal will not settle within the cycle time (T).Solutions: SynchronizersCLK ACLK BDDAWe want the metastability to dissipate at least tsetupbefore the next clock edge, so: What is the probability of failure?The probability for metastability to pass is: ()SP tSe=with τa parameter of the flip flop()()()setupfailuremetaexitTtwTPPPeT==And the mean time between failures (MTBF) is the inverse of the failure rate:()setup11failureTtDwMTBFeRateffT==For our previous example, this is about 1024years
52©Adam Teman, 2018Are synchronizers enough?No!We may have taken care of metastability, but data loss and data incoherence are still there.So we need to design our logicaccordingly.To eliminate data loss:Slowto fastclock we wont lose any data.Fastto slowclock hold source data for several cycles.But for data coherence, we need more thinking:Handshake protocols.First-in First-out (FIFO) interfacesOther solutions (Gray code, Multiplexers, etc.)Source: ZipCPU.com
53©Adam Teman, 2018Main ReferencesBerkeley EE141RabaeyDigital Integrated CircuitsSynopsys University CoursewareIDESAGil RahavDennis Sylvester, UMICHMIT 6.375 Complex Digital SystemsHorowitz, StanfordGinosar, Metastability and Synchronizers: A Tutorial

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