All of the tasks were run on commodity general purpose hardware platforms

All of the tasks were run on commodity general

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bulk data transfer, networking, and time synchronization. All of the tasks were run on commodity, general-purpose hardware platforms without any hardware acceleration for the more frequent tasks. 3. CIRCUIT DESIGN TECHNIQUES Several layers below the application, the circuits layer con- tains many opportunities to reduce power consumption. WSNs with low computation requirements are idle most of the time, so leakage current makes up the largest frac- tion of overall energy consumption. Moreover, as process technology dimensions scale, leakage current increases. In this section we describe circuit techniques which have been used to reduce energy consumption in WSN nodes. 3.1. Voltage and Frequency Scaling and Subthreshold Design Sensor network applications are untethered from wired power sources, therefore conserving system energy con- sumption is the primary design concern. Energy can be expressed as the sum of active switching energy plus leak- age current energy. 1 E total = V dd C sw V dd + I leak t op (1) Where is the switching activity for one second and t op is the amount of time required to complete an oper- ation. For low duty cycle applications, leakage energy will dominate because will be small. One of the most effective ways to save energy is to scale the power sup- ply voltage. As V dd scales down, active energy decreases quadratically. As pointed out in the literature, there is an energy optimal point for V dd that for most circuits is less than the threshold voltage ( V th ). The main concern when lowering V dd is that traditional SRAMs do not operate reliably below V th . A few recent subthreshold SRAM pro- totypes have shown potential, but the designs are not yet ready for full-scale production. 2 The relationship between supply voltage and delay is a major concern when operating circuits in subthresh- old. The drive current of a transistor operating in sub- threshold is exponentially related to the supply voltage. Consequently, delay of a CMOS gate in subthreshold can be represented by the simple expression: t op e kV dd (2) where k is a constant that depends on technology and tem- perature. Circuit delay will vary exponentially with any J. Low Power Electronics 4, 1–10, 2008 3
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Survey of Hardware Systems for Wireless Sensor Networks Hempstead et al. variation in manufacturing or temperature, so selecting a fixed clock frequency where the chip will operate reli- ably can be difficult. As described in Section 2, compu- tation requirements of WSN applications vary by several orders of magnitude. Synchronous subthreshold systems that run at low clock frequencies might not be able to meet the computation requirements of mid and high frequency sample rates. Subthreshold operation provides significant energy savings at the cost of performance and are suitable for WSN workloads that do not require significant compu- tational resources.
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  • Fall '18
  • Mr. Bhullar
  • Sensor node, Wireless sensor network

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